Research

The microarchitecture of a multi-threaded RISC-V compliant processing core family for IoT end-nodes

Abstract This paper presents the microarchitecture of an open-source, multi-threaded processing core family designed for low-power Internet-of-Things (IoT) end-nodes. The core is fully compliant with the RISC-V instruction set and maintains hardware compatibility

By Admin 13 Dec 2017 • 2 min read •

Research

Princeton finds bugs in RISC-V architecture ... - eeNews Europe

Abstract Researchers at Princeton University have identified significant architectural vulnerabilities or 'bugs' within the open-source RISC-V Instruction Set Architecture (ISA) specification. This discovery, covered by eeNews Europe, emphasizes the importance of

By Admin 19 Apr 2017 • 1 min read •

Research

System Bits: April 18 - Semiconductor Engineering

Abstract This analysis focuses on the technical scope anticipated for a "System Bits" compilation published by Semiconductor Engineering, as the full article text was not accessible via the provided citation. These

By Admin 18 Apr 2017 • 1 min read •

Research

Tool for checking complex computer architectures reveals flaws in emerging design - Princeton University

Abstract Princeton University researchers developed a novel formal verification tool designed to check the integrity and specification correctness of complex computer architectures. When applied to an emerging chip design, the tool successfully uncovered

By Admin 12 Apr 2017 • 2 min read •

Research

Epiphany-V: A 1024 processor 64-bit RISC System-On-Chip

Abstract The Epiphany-V project details the design of a highly parallel System-On-Chip featuring 1024 64-bit RISC processors fabricated using 16nm FinFET technology. This massively multi-core architecture integrates 64MB of on-chip SRAM and utilizes

By Admin 6 Oct 2016 • 1 min read •

Research

Colombia designs 32-bit MCU based on RISC-V - EE Times Asia

Originally published on Google News - RISC-V Research Colombia designs 32-bit MCU based on RISC-V  EE Times Asia

By Admin 19 Sep 2016 •

Research

A near-threshold RISC-V core with DSP extensions for scalable IoT Endpoint Devices

Abstract This paper presents the design of an open-source RISC-V processor core optimized for Near-Threshold (NT) operation within scalable multi-core clusters targeting energy-constrained IoT endpoint devices. The core integrates instruction extensions for Digital

By Admin 30 Aug 2016 • 2 min read •

Research

TriCheck: Memory Model Verification at the Trisection of Software, Hardware, and ISA

Abstract Memory Consistency Models (MCMs) are typically verified in isolation across the hardware-software stack, leading to unverified interactions between compilers, ISA, and hardware implementations. TriCheck is a novel toolflow designed for full-stack MCM

By Admin 26 Aug 2016 • 2 min read •

Research

The Renewed Case for the Reduced Instruction Set Computer: Avoiding ISA Bloat with Macro-Op Fusion for RISC-V

Abstract This paper renews the argument for Reduced Instruction Set Computers (RISC), demonstrating that the open RISC-V ISA, particularly its compressed variant (RV64GC), can achieve performance and code density superior to complex proprietary

By Admin 8 Jul 2016 • 2 min read •

Research

A Soft Processor Overlay with Tightly-coupled FPGA Accelerator

Abstract This paper presents an open-source soft processor designed for tight integration within an FPGA overlay framework to facilitate full application acceleration. Leveraging the RISC-V instruction set and a 4-stage pipeline, the design

By Admin 21 Jun 2016 • 2 min read •

Research

GRVI Phalanx: A Massively Parallel RISC-V FPGA Accelerator Accelerator

Abstract GRVI Phalanx is a massively parallel framework combining the FPGA-efficient RISC-V RV32I soft processor (GRVI) with a high-density parallel processor and accelerator array (Phalanx). This architecture utilizes shared memory clusters interconnected by

By Admin 3 Jun 2016 • 2 min read •

Research

Using System Hyper Pipelining (SHP) to Improve the Performance of a Coarse-Grained Reconfigurable Architecture (CGRA) Mapped on an FPGA

Abstract This paper introduces System Hyper Pipelining (SHP), an advanced extension of C-Slow Retiming, applied to the Programming Elements (PEs) of a Coarse-Grained Reconfigurable Architecture (CGRA). SHP enables dynamic management of execution threads—

By Admin 28 Aug 2015 • 2 min read •