Research

Fast TLB Simulation for RISC-V Systems

Abstract This paper introduces a novel, fast TLB simulation framework specifically designed for exploring Translation Lookaside Buffer (TLB) behaviors in multi-core RISC-V systems. Integrated into the QEMU dynamic binary translated emulator, the framework

By Admin 16 May 2019 • 2 min read •

Research

The Cost of Application-Class Processing: Energy and Performance Analysis of a Linux-ready 1.7GHz 64bit RISC-V Core in 22nm FDSOI Technology

Abstract This paper presents a thorough energy and performance analysis of Ariane, an open-source, single-issue 64-bit RISC-V core implemented for application-class processing and supporting the Linux OS. Taped-out in 22nm FDSOI technology, the

By Admin 10 Apr 2019 • 2 min read •

Research

Formal Verification Of RISC-V Cores - Semiconductor Engineering

Abstract The article emphasizes the critical role of Formal Verification (FV) in the development lifecycle of RISC-V cores, ensuring functional correctness and adherence to the Instruction Set Architecture (ISA). It details how FV

By Admin 28 Feb 2019 • 2 min read •

Research

NTX: An Energy-efficient Streaming Accelerator for Floating-point Generalized Reduction Workloads in 22nm FD-SOI

Abstract NTX is an energy-efficient streaming accelerator designed for 32-bit floating-point generalized reduction workloads, including training large Deep Neural Networks. Implemented in 22nm FD-SOI technology and orchestrated by a RISC-V core, the accelerator

By Admin 1 Dec 2018 • 2 min read •

Research

JuxtaPiton: Enabling Heterogeneous-ISA Research with RISC-V and SPARC FPGA Soft-cores

Abstract JuxtaPiton is introduced as the first open-source, general-purpose, heterogeneous-ISA processor designed to enable crucial energy efficiency research. It integrates a small RISC-V core alongside a modified OpenSPARC T1 core within the OpenPiton

By Admin 20 Nov 2018 • 1 min read •

Research

Formally Verifying WARP-V, an Open-Source TL-Verilog RISC-V Core Generator

Abstract This paper details the formal verification of WARP-V, an open-source RISC-V core generator developed using the timing-abstract, transaction-level TL-Verilog methodology. The verification employed the established riscv-formal framework, investigating the synergy between transaction-level

By Admin 5 Nov 2018 • 1 min read •

Research

RISC-V: More Than a Core - Semiconductor Engineering

Abstract The article analyzes the maturation of the RISC-V ecosystem, arguing that its impact now extends far beyond the foundational Instruction Set Architecture (ISA). It emphasizes the critical role of surrounding elements, including

By Admin 15 Oct 2018 • 2 min read •

Research

CIDPro: Custom Instructions for Dynamic Program Diversification

Abstract CIDPro is a novel framework that uses dynamic program diversification and custom instruction generation to mitigate timing side-channel attacks in embedded systems. It integrates the LLVM compiler and the RISC-V FPGA soft-processor,

By Admin 4 Sep 2018 • 2 min read •

Research

The BaseJump Manycore Accelerator Network

Abstract The BaseJump Manycore Accelerator Network is an open-source, mesh-based On-Chip-Network (OCN) developed using over 20 years of manycore architecture expertise. This scalable network served as the communication backbone for the 16nm 511-core

By Admin 2 Aug 2018 • 2 min read •

Research

A Scalable Near-Memory Architecture for Training Deep Neural Networks on Large In-Memory Datasets

Abstract This paper proposes NTX, a scalable near-memory acceleration engine designed for high-precision training of deep neural networks, moving beyond the traditional focus on inference acceleration. NTX is implemented on the Logic Base

By Admin 19 Feb 2018 • 2 min read •

Research

Instruction-Level Abstraction (ILA): A Uniform Specification for System-on-Chip (SoC) Verification

Abstract Modern Systems-on-Chip (SoC) designs require a new verification standard due to their heterogeneity and reliance on specialized accelerators, which traditional Instruction Set Architectures (ISA) fail to cover. This paper formalizes the Instruction-Level

By Admin 3 Jan 2018 • 2 min read •

Research

HERO: Heterogeneous Embedded Research Platform for Exploring RISC-V Manycore Accelerators on FPGA

Abstract HERO is an FPGA-based heterogeneous embedded research platform designed to combine an industry-standard host processor with an open, scalable programmable manycore accelerator (PMCA). The platform integrates a hard ARM Cortex-A multicore host

By Admin 18 Dec 2017 • 2 min read •