Research

A portable and Linux capable RISC-V computer system in Verilog HDL

Abstract This paper introduces a novel, portable RISC-V computer system implemented entirely in Verilog HDL, explicitly designed to boot the Linux operating system. Addressing the scarcity of public, Linux-capable RISC-V systems, the proposed

By Admin 10 Feb 2020 • 1 min read •

Research

RVCoreP : An optimized RISC-V soft processor of five-stage pipelining

Abstract RVCoreP is an optimized five-stage pipelined soft processor designed for FPGAs, implementing the RISC-V 32-bit Integer (RV32I) instruction set architecture. The processor incorporates three key optimization techniques focusing on instruction fetch/branch

By Admin 10 Feb 2020 • 1 min read •

Research

SSR: A Stall Scheme Reducing Bubbles in Load-Use Hazard of RISC-V Pipeline

Abstract This paper introduces SSR (Stall Scheme Reducing bubbles), a microarchitectural modification designed to reduce performance degradation caused by load-use hazards in RISC-V pipelines. The proposed method replaces the traditional ID-EXE stage stall

By Admin 23 Dec 2019 • 2 min read •

Research

Stream Semantic Registers: A Lightweight RISC-V ISA Extension Achieving Full Compute Utilization in Single-Issue Cores

Abstract Stream Semantic Registers (SSR) is a lightweight, non-invasive RISC-V Instruction Set Architecture extension designed to overcome the von Neumann bottleneck in energy-efficient single-issue cores. SSR achieves full compute utilization by implicitly encoding

By Admin 19 Nov 2019 • 2 min read •

Research

Using Name Confusion to Enhance Security

Abstract The paper introduces Name Confusion, a novel security concept implemented by the Phantom Name System (PNS), designed to thwart multiple classes of code-reuse attacks. PNS provides multiple randomized virtual addresses (N mappings)

By Admin 5 Nov 2019 • 2 min read •

Research

Sapphire: A Configurable Crypto-Processor for Post-Quantum Lattice-based Protocols

Abstract Sapphire is a configurable crypto-processor designed to accelerate computationally intensive lattice-based post-quantum cryptography (PQC) protocols on low-power embedded devices. Utilizing optimizations such as a SHA-3-based PRNG and a single-port RAM NTT memory

By Admin 16 Oct 2019 • 2 min read •

Research

Researchers build first 16-bit, 14,000-transistor carbon nanotube chip - bit-tech.net

Abstract Researchers have successfully engineered the world's first 16-bit microprocessor built entirely using carbon nanotube (CNT) technology. This groundbreaking chip integrates 14,000 transistors, marking a significant milestone in demonstrating the

By Admin 29 Aug 2019 • 1 min read •

Research

Researchers build first 16-bit, 14,000-transistor carbon nanotube chip - Bit-Tech

Originally published on Google News - RISC-V Research Researchers build first 16-bit, 14,000-transistor carbon nanotube chip  Bit-Tech

By Admin 29 Aug 2019 •

Research

BRISC-V: An Open-Source Architecture Design Space Exploration Toolbox

Abstract BRISC-V is an open-source, parameterized, and synthesizable register-transfer level (RTL) platform designed for comprehensive architecture design space exploration of RISC-V systems. It provides highly modular components spanning simple single-core designs to complex

By Admin 27 Aug 2019 • 2 min read •

Research

Boosting the Bounds of Symbolic QED for Effective Pre-Silicon Verification of Processor Cores

Abstract This work introduces a novel pre-silicon verification approach that systematically leverages Symbolic Quick Error Detection (SQED) combined with symbolic starting states to drastically improve the detection of deep logic bugs and Hardware

By Admin 19 Aug 2019 • 2 min read •

Research

PERI: A Posit Enabled RISC-V Core

Abstract This paper introduces PERI, the first Posit Enabled RISC-V core, which integrates the advanced Posit arithmetic format—a superior alternative to IEEE 754—into the extensible RISC-V ISA. The implementation leverages the

By Admin 5 Aug 2019 • 2 min read •

Research

Ara: A 1 GHz+ Scalable and Energy-Efficient RISC-V Vector Processor with Multi-Precision Floating Point Support in 22 nm FD-SOI

Abstract Ara is a highly scalable and energy-efficient 64-bit vector processor based on the RISC-V vector extension (v0.5 draft), realized in 22 nm FD-SOI technology. Its lane-based microarchitecture achieves clock speeds exceeding

By Admin 2 Jun 2019 • 2 min read •