Research

Klessydra-T: Designing Vector Coprocessors for Multi-Threaded Edge-Computing Cores

Abstract Klessydra-T investigates methodologies for designing vector coprocessors tailored for Interleaved-Multi-Threading (IMT) RISC-V cores targeting edge-computing applications. The core goal is to efficiently accelerate computation-intensive kernels, such as AI convolutions and matrix multiplication,

By Admin 17 Jul 2020 • 2 min read •

Research

Enabling Mixed-Precision Quantized Neural Networks in Extreme-Edge Devices

Abstract This work introduces a critical extension to the PULP-NN library optimized for accelerating mixed-precision Quantized Neural Networks (QNNs) on ultra-low-power RISC-V edge devices. Featuring 27 highly optimized kernels supporting 8-bit, 4-bit, and

By Admin 15 Jul 2020 • 2 min read •

Research

The gem5 Simulator: Version 20.0+

Abstract This paper introduces the gem5 Simulator: Version 20.0+, detailing the evolution of this popular open-source computer architecture research tool over the last nine years. The simulator provides high-fidelity, cycle-level modeling capable

By Admin 7 Jul 2020 • 2 min read •

Research

FPnew: An Open-Source Multi-Format Floating-Point Unit Architecture for Energy-Proportional Transprecision Computing

Abstract FPnew is a highly configurable, open-source transprecision floating-point unit (TP-FPU) architecture designed to enable energy-proportional computing by handling a wide range of standard and custom FP formats. The unit extends the RISC-V

By Admin 3 Jul 2020 • 2 min read •

Research

Arnold: an eFPGA-Augmented RISC-V SoC for Flexible and Low-Power IoT End-Nodes

Abstract Arnold is an energy-efficient, flexible RISC-V System-on-Chip (SoC) designed for demanding IoT end-nodes, coupling a high-performance MCU with an embedded FPGA (eFPGA) in 22nm GF22FDX technology. The SoC achieves exceptional power efficiency

By Admin 25 Jun 2020 • 2 min read •

Research

CLARINET: A RISC-V Based Framework for Posit Arithmetic Empiricism

Abstract CLARINET is an open-source, RISC-V based processor framework designed for the empirical validation of posit arithmetic as a potential replacement for the IEEE 754 floating-point standard. The framework incorporates 'Melodica,'

By Admin 30 May 2020 • 2 min read •

Research

Accelerate Cycle-Level Full-System Simulation of Multi-Core RISC-V Systems with Binary Translation

Abstract This paper presents a novel multi-purpose simulator that accelerates cycle-level full-system simulation of multi-core RISC-V systems using binary translation. The tool successfully addresses the perennial trade-off between simulation accuracy and performance, achieving

By Admin 22 May 2020 • 1 min read •

Research

A Lightweight Isolation Mechanism for Secure Branch Predictors

Abstract This paper presents a lightweight, randomization-based mechanism to isolate content within shared branch predictors, counteracting cross-process malicious training and perception attacks. The solution avoids performance-heavy methods like flushing or physical isolation by

By Admin 17 May 2020 • 2 min read •

Research

LiteX: an open-source SoC builder and library based on Migen Python DSL

Abstract LiteX is an open-source, BSD-licensed SoC builder and IP library designed for creating full FPGA designs and Systems-on-Chip. Its originality lies in describing all IP components entirely using the Migen Python Internal

By Admin 5 May 2020 • 2 min read •

Research

Prevention of Microarchitectural Covert Channels on an Open-Source 64-bit RISC-V Core

Abstract This paper addresses the prevention of microarchitectural covert channels that exploit shared hardware resources to leak information across OS security boundaries, focusing on the open-source 64-bit RISC-V Ariane core. Initial attempts using

By Admin 1 May 2020 • 2 min read •

Research

Energy-Efficient Hardware-Accelerated Synchronization for Shared-L1-Memory Multiprocessor Clusters

Abstract This paper proposes a light-weight Hardware-Accelerated Synchronization and Communication Unit (SCU) designed for shared-L1-memory multiprocessor clusters operating under energy-efficient near-threshold computing (NTC) conditions. Integrated into an eight-core RISC-V cluster, the SCU significantly

By Admin 14 Apr 2020 • 2 min read •

Research

Cycle-Accurate Evaluation of Software-Hardware Co-Design of Decimal Computation in RISC-V Ecosystem

Abstract This paper presents a cycle-accurate evaluation framework for software-hardware co-design solutions targeting decimal computation within the RISC-V ecosystem. The methodology involves integrating dedicated hardware, realized as an accelerator supporting new decimal-oriented instructions,

By Admin 11 Mar 2020 • 1 min read •