Research

Indirection Stream Semantic Register Architecture for Efficient Sparse-Dense Linear Algebra

Abstract This work introduces the Indirection Stream Semantic Register Architecture, an enhancement to a memory-streaming RISC-V ISA extension designed to efficiently handle sparse-dense linear algebra, which traditionally suffers from indirect memory lookup bottlenecks.

By Admin 16 Nov 2020 • 2 min read •

Research

RVCoreP-32IM: An effective architecture to implement mul/div instructions for five stage RISC-V soft processors

Abstract The RVCoreP-32IM architecture is proposed as an effective extension to the five-stage RVCoreP soft processor to efficiently implement the RISC-V M-extension (multiplication/division instructions). Utilizing a simple fork-join method to expand execution

By Admin 30 Oct 2020 • 1 min read •

Research

The nanoPU: Redesigning the CPU-Network Interface to Minimize RPC Tail Latency

Abstract The nanoPU is a new CPU architecture optimized for networking tasks, specifically designed to minimize tail latency for Remote Procedure Calls (RPCs). It achieves an extremely fast 65ns wire-to-wire latency—a 13x

By Admin 23 Oct 2020 • 2 min read •

Research

Composite Enclaves: Towards Disaggregated Trusted Execution

Abstract Trusted Execution Environments (TEEs) traditionally fail to protect code leveraging specialized or disaggregated heterogeneous hardware outside the main CPU, due to their fixed hardware Trusted Computing Base (TCB). This paper proposes "

By Admin 20 Oct 2020 • 2 min read •

Research

A RISC-V SystemC-TLM simulator

Abstract This work presents a SystemC-TLM based simulator for a RISC-V microcontroller, prioritizing simplicity and expandability for System-on-Chip (SoC) development. It integrates a full RISC-V Instruction Set Simulator (ISS) supporting key ISA extensions,

By Admin 20 Oct 2020 • 2 min read •

Research

Elasticlave: An Efficient Memory Model for Enclaves

Abstract Elasticlave proposes a novel memory model for Trusted Execution Environments (TEEs) that overcomes the severe performance penalties associated with traditional spatial isolation models like Intel SGX. This innovation allows enclaves to selectively

By Admin 16 Oct 2020 • 2 min read •

Research

A Mixed-Precision RISC-V Processor for Extreme-Edge DNN Inference

Abstract This work introduces the MPIC (Mixed Precision Inference Core), a novel RISC-V processor designed to efficiently execute fine-grained mixed-precision Quantized Neural Networks (QNNs) on extreme-edge microcontrollers. It solves the challenge of supporting

By Admin 8 Oct 2020 • 2 min read •

Research

An Embedded RISC-V Core with Fast Modular Multiplication

Abstract This work introduces an embedded RISC-V core designed to address the security and power consumption challenges inherent in battery-operated IoT devices by accelerating cryptographic operations. The key innovation is an extended custom

By Admin 30 Sep 2020 • 2 min read •

Research

Enabling Virtual Memory Research on RISC-V with a Configurable TLB Hierarchy for the Rocket Chip Generator

Abstract This work enhances the RISC-V Rocket Chip Generator by implementing a configurable, set-associative Translation Lookaside Buffer (TLB) hierarchy within its Memory Management Unit. This innovation lifts the previous restrictions of fixed L1/

By Admin 16 Sep 2020 • 2 min read •

Research

A transprecision floating-point cluster for efficient near-sensor data analytics

Abstract This paper presents a multi-core computing cluster based on the open-source RISC-V architecture, utilizing transprecision floating-point arithmetic for efficient near-sensor data analytics. The system achieves a minimum power budget through parallelization, sub-word

By Admin 27 Aug 2020 • 2 min read •

Research

Manticore: A 4096-core RISC-V Chiplet Architecture for Ultra-efficient Floating-point Computing

Abstract Manticore is a 4096-core RISC-V chiplet architecture designed for ultra-efficient, general-purpose data-parallel floating-point (FP) workloads. It utilizes Snitch clusters, where small integer cores control large FPUs, achieving FPU utilization above 90% through

By Admin 14 Aug 2020 • 2 min read •

Research

BasicBlocker: ISA Redesign to Make Spectre-Immune CPUs Faster

Abstract This paper introduces BasicBlocker, a novel ISA redesign that enables non-speculative CPUs to achieve performance comparable to systems utilizing speculative execution, thereby addressing Spectre-class attacks robustly. BasicBlocker is a generic modification applicable

By Admin 31 Jul 2020 • 2 min read •