News

Intel ISPC 1.29 Drops Gen9 GPU Targets, Add New Optimizations & Experimental RISC-V - Phoronix

Abstract Intel has released version 1.29 of its Implicit SPMD Program Compiler (ISPC), marking a significant update that focuses on modernization and architecture expansion. The release notably discontinues support for older Gen9

By Admin 18 Dec 2025 • 2 min read •

Research

A Brief History of Formal Methods in China

Abstract This article details the historical trajectory and evolution of formal methods (FM) research and practical application within the technological landscape of China. It chronicles key academic milestones, influential research institutions, and major

By Admin 18 Dec 2025 • 2 min read •

News

RISC-V vs. Arm & x86: AI Drives Open-Source Chip Shift | 2025 Analysis - News and Statistics - IndexBox

Abstract The analysis forecasts a significant open-source chip shift driven by AI acceleration, positioning the customizable RISC-V architecture as a powerful challenger to established proprietary instruction sets like Arm and x86. By 2025,

By Admin 18 Dec 2025 • 2 min read •

News

Newer RISC-V CPUs Vulnerable To Spectre V1 - Linux Mitigation Patches Posted - Phoronix

Abstract Newer, high-performance RISC-V CPUs have been confirmed vulnerable to the classic Spectre Variant 1 (V1) speculative execution side-channel attack. This discovery highlights that RISC-V implementations adopting modern performance features, such as deep

By Admin 18 Dec 2025 • 2 min read •

Research

ChatArch: A Knowledge-driven Graph-of-thought LLM Framework for Processor Architecture Optimization

Abstract ChatArch introduces a novel Knowledge-driven Graph-of-thought (GoT) LLM framework designed to automate and optimize the challenging process of processor architecture design. By integrating domain-specific knowledge graphs, ChatArch facilitates structured, multi-path reasoning for

By Admin 17 Dec 2025 • 2 min read •

News

Co-emulation platform targets complex RISC-V chip design - Engineering.com

Abstract A newly introduced co-emulation platform is specifically engineered to handle the high complexity and customizability inherent in advanced RISC-V chip designs. This verification solution integrates high-speed hardware emulation with software simulation, enabling

By Admin 17 Dec 2025 • 2 min read •

News

Co-emulation platform targets complex RISC-V chip design - Engineering.com

Abstract A newly introduced co-emulation platform is specifically engineered to handle the high complexity and customizability inherent in advanced RISC-V chip designs. This verification solution integrates high-speed hardware emulation with software simulation, enabling

By Admin 17 Dec 2025 • 2 min read •

News

Tenstorrent advances RISC-V AI chips in China with former Arm China CEO - DIGITIMES Asia

Originally published on Google News - RISC-V Tenstorrent advances RISC-V AI chips in China with former Arm China CEO  DIGITIMES Asia

By Admin 17 Dec 2025 •

News

SiFive and IAR strengthen RISC-V automotive toolchain ... - eeNews Europe

Abstract SiFive and IAR Systems have announced a collaboration aimed at significantly enhancing the RISC-V automotive toolchain. This partnership integrates IAR's certified Embedded Workbench with SiFive's automotive processor IP,

By Admin 17 Dec 2025 • 2 min read •

News

Tenstorrent advances RISC-V AI chips in China with former Arm China CEO - digitimes

Abstract Tenstorrent is strategically advancing its RISC-V AI chip initiative within the crucial Chinese market. This expansion is bolstered by the involvement of the former CEO of Arm China, signaling a high-profile move

By Admin 17 Dec 2025 • 2 min read •

News

India unveils a homegrown dual-core 1GHz RISC-V processor, the DHRUV64 - theregister.com

Abstract India has unveiled the DHRUV64, an indigenously developed dual-core processor utilizing the open-source RISC-V architecture. This chip operates at a clock speed of 1GHz, signaling a major step toward India’s goal

By Admin 17 Dec 2025 • 1 min read •

News

Breakingviews - AI’s 2026 dark horse will be open-standard chips - Reuters

Abstract The Reuters Breakingviews article predicts that open-standard chips, most notably those based on architectures like RISC-V, will emerge as the unexpected 'dark horse' in the AI hardware market by 2026.

By Admin 17 Dec 2025 • 2 min read •