Research

RISC-V Targets Data Centers - Semiconductor Engineering

Abstract RISC-V is actively targeting the data center market, transitioning from embedded systems to challenge established server architectures by focusing on customization and efficiency for demanding workloads. The open instruction set architecture (ISA)

By Admin 22 Apr 2021 • 2 min read •

Research

CodeAPeel: An Integrated and Layered Learning Technology For Computer Architecture Courses

Abstract CodeAPeel is a novel, multi-layered learning technology for computer architecture courses that simulates instruction processing across compiler, assembly, and machine layers. Unlike simulators modeling real processors (e.g., RISC-V), CodeAPeel utilizes a

By Admin 18 Apr 2021 • 1 min read •

Research

A First Look at RISC-V Virtualization from an Embedded Systems Perspective

Abstract This article describes the first public implementation and evaluation of the RISC-V Hypervisor Extension (H-extension v0.6.1) targeting embedded and mixed-criticality systems on a Rocket chip core. The work successfully ported

By Admin 27 Mar 2021 • 2 min read •

Research

Comparative Analysis and Enhancement of CFG-based Hardware-Assisted CFI Schemes

Abstract This paper addresses the difficulty of quantitatively comparing existing hardware-assisted Control Flow Integrity (CFI) schemes by implementing several promising CFG-based mechanisms on a unified RISC-V platform. The authors benchmark performance, hardware utilization,

By Admin 7 Mar 2021 • 2 min read •

Research

Open Source RISC-V Hardware Changes the Game - EE Times Asia

Abstract The shift towards open-source RISC-V hardware is fundamentally transforming the semiconductor industry by democratizing processor design and development. This open Instruction Set Architecture (ISA) facilitates rapid innovation, enabling unprecedented customization and drastically

By Admin 4 Feb 2021 • 2 min read •

Research

Brightening the Optical Flow through Posit Arithmetic

Abstract This paper investigates the commercial and technical merits of the posit data format as a drop-in replacement for the IEEE 754 floating-point standard, specifically applying it to the Lucas-Kanade (LuKa) optical flow

By Admin 17 Jan 2021 • 2 min read •

Research

ANDROMEDA: An FPGA Based RISC-V MPSoC Exploration Framework

Abstract ANDROMEDA is an FPGA-based framework designed for the exploration and optimization of complex RISC-V Multiprocessor Systems-on-Chip (MPSoCs). It enables computer architects to vary and observe the performance trade-offs of critical parameters, including

By Admin 14 Jan 2021 • 1 min read •

Research

Efficient Sealable Protection Keys for RISC-V

Abstract This paper proposes SealPK, an efficient hardware-assisted intra-process isolation mechanism for the RISC-V open ISA, designed to overcome limitations found in modern processors like Intel MPK. SealPK dramatically expands domain capacity to

By Admin 4 Dec 2020 • 2 min read •

Research

XpulpNN: Enabling Energy Efficient and Flexible Inference of Quantized Neural Network on RISC-V based IoT End Nodes

Abstract XpulpNN introduces lightweight RISC-V ISA extensions supporting 4-bit and 2-bit SIMD instructions to accelerate heavily Quantized Neural Network (QNN) inference on IoT end nodes. The architecture utilizes a parallel cluster of 8

By Admin 29 Nov 2020 • 2 min read •

Research

RVCoreP-32IC: A high-performance RISC-V soft processor with an efficient fetch unit supporting the compressed instructions

Abstract This paper proposes RVCoreP-32IC, a high-performance RISC-V soft processor targeting FPGAs, featuring a novel instruction fetch unit engineered to efficiently support compressed instructions (RVC). Although RVC reduces code size by about 25%

By Admin 23 Nov 2020 • 2 min read •

Research

SIMF: Single-Instruction Multiple-Flush Mechanism for Processor Temporal Isolation

Abstract Microarchitectural timing attacks exploit shared on-core state components like caches and TLBs, which are traditionally mitigated inefficiently using software-based flushing instructions. This paper introduces SIMF (Single-Instruction Multiple-Flush), a specialized hardware mechanism implemented

By Admin 20 Nov 2020 • 2 min read •

Research

AXES: Approximation Manager for Emerging Memory Architectures

Abstract AXES is the first self-optimizing runtime manager designed to coordinate configurable approximation knobs across all levels of the memory hierarchy, overcoming the limitations of rigid, design-time policies. It continuously learns and updates

By Admin 17 Nov 2020 • 2 min read •