Research

Is RISC-V The Future? - Semiconductor Engineering

Abstract The Semiconductor Engineering analysis titled 'Is RISC-V The Future?' evaluates the rapidly expanding role of the open-source RISC-V Instruction Set Architecture (ISA) across the semiconductor industry. It examines RISC-V’s

By Admin 29 Jul 2021 • 2 min read •

Research

A natively flexible 32-bit Arm microprocessor - Nature

Abstract Researchers have successfully engineered a natively flexible 32-bit Arm microprocessor, transitioning complex, high-performance computing onto flexible substrates. This innovation integrates a powerful 32-bit instruction set architecture into bendable electronics, achieving reliable operation

By Admin 21 Jul 2021 • 2 min read •

Research

Arrow: A RISC-V Vector Accelerator for Machine Learning Inference

Abstract This paper introduces Arrow, a configurable hardware accelerator architecture implementing a subset of the RISC-V v0.9 vector ISA extension, specifically targeting edge machine learning inference. Benchmarked against fundamental vector and matrix

By Admin 15 Jul 2021 • 1 min read •

Research

A Survey on RISC-V Security: Hardware and Architecture

Abstract This paper presents the first comprehensive survey of security solutions for the open RISC-V Instruction Set Architecture (ISA), addressing a critical research gap in the rapidly evolving IoT landscape. It analyzes representative

By Admin 9 Jul 2021 • 2 min read •

Research

Flare: Flexible In-Network Allreduce

Abstract Flare is a flexible programmable switch designed to accelerate the computationally intensive allreduce communication operation in distributed systems by offloading aggregation to the network. Existing in-network solutions lack customization for specific data

By Admin 29 Jun 2021 • 2 min read •

Research

Effective Pre-Silicon Verification of Processor Cores by Breaking the Bounds of Symbolic Quick Error Detection

Abstract This paper introduces a novel pre-silicon verification approach that extends Symbolic Quick Error Detection (SQED) by incorporating symbolic starting states, effectively breaking the bounds of conventional verification. This methodology allows Bounded Model

By Admin 18 Jun 2021 • 2 min read •

Research

Towards Accurate Performance Modeling of RISC-V Designs

Abstract This paper investigates the critical challenge of achieving high performance modeling accuracy using microarchitecture-level simulators, which traditionally prioritize speed over fidelity compared to RTL simulation. The authors conduct a detailed study using

By Admin 18 Jun 2021 • 2 min read •

Research

Side-Channel Attacks on RISC-V Processors: Current Progress, Challenges, and Opportunities

Abstract This paper presents a comprehensive study of security vulnerabilities in modern RISC-V microprocessors stemming from side-channel attacks (SCAs) and their corresponding mitigation techniques. The analysis focuses on both hardware-exploitable attacks, specifically using

By Admin 16 Jun 2021 • 2 min read •

Research

Extending the RISC-V ISA for exploring advanced reconfigurable SIMD instructions

Abstract This paper presents a novel set of non-standard vector instruction types designed to extend the RISC-V ISA for exploring advanced, reconfigurable SIMD operations. The authors introduce a high-performance, open-source RV32 IM softcore

By Admin 14 Jun 2021 • 2 min read •

Research

Isadora: Automated Information Flow Property Generation for Hardware Designs

Abstract Isadora is an automated methodology designed to generate information flow specifications for hardware designs, eliminating the need for manual security specifications or threat models. It operates by combining information flow tracking and

By Admin 14 Jun 2021 • 2 min read •

Research

HeapSafe: Securing Unprotected Heaps in RISC-V

Abstract HeapSafe is a novel, lightweight hardware-assisted security scheme designed to mitigate critical memory corruption vulnerabilities, such as heap overflow and use-after-free, in bare-metal RISC-V systems. The approach utilizes a configurable coprocessor, decoupled

By Admin 18 May 2021 • 2 min read •

Research

MetaSys: A Practical Open-Source Metadata Management System to Implement and Evaluate Cross-Layer Optimizations

Abstract MetaSys is the first open-source, FPGA-based infrastructure, prototyped within a RISC-V core, designed to enable the rapid implementation and evaluation of diverse cross-layer hardware-software optimizations. It introduces a lightweight, generalized metadata management

By Admin 17 May 2021 • 2 min read •