Research

IMCRYPTO: An In-Memory Computing Fabric for AES Encryption and Decryption

Abstract IMCRYPTO is a novel In-Memory Computing (IMC) fabric designed to accelerate AES encryption and decryption using a unified hardware architecture. This approach combines the (Inv)SubBytes and (Inv)MixColumns steps, leveraging high

By Admin 4 Dec 2021 • 2 min read •

Research

PERCIVAL: Open-Source Posit RISC-V Core with Quire Capability

Abstract PERCIVAL is the first open-source, application-level RISC-V core to natively implement the complete posit arithmetic instruction set, critically including the quire fused operations. This implementation integrates the Xposit RISC-V extension into LLVM,

By Admin 30 Nov 2021 • 1 min read •

Research

G-GPU: A Fully-Automated Generator of GPU-like ASIC Accelerators

Abstract G-GPU introduces a general-purpose, GPU-like ASIC accelerator designed for energy-efficient, high-performance parallel processing in Systems on Chip (SoCs). The core innovation is GPUPlanner, an open-source, fully-automated platform that generates these complex accelerators

By Admin 11 Nov 2021 • 2 min read •

Research

vlang: Mapping Verilog Netlists to Modern Technologies

Abstract This paper introduces vlang, a novel framework designed to solve the challenge of migrating device-specific Verilog netlists to modern computational targets when original design files are unavailable. vlang automatically translates these netlists

By Admin 9 Nov 2021 • 2 min read •

Research

PiDRAM: A Holistic End-to-end FPGA-based Framework for Processing-in-DRAM

Abstract PiDRAM is presented as the first flexible, end-to-end FPGA-based framework designed to solve system integration challenges for Processing-using-Memory (PuM) techniques on off-the-shelf DRAM. Utilizing an open-source RISC-V system, the framework provides comprehensive

By Admin 29 Oct 2021 • 2 min read •

Research

A RISC-V Simulator and Benchmark Suite for Designing and Evaluating Vector Architectures

Abstract Vector architecture research currently suffers from a critical lack of flexible simulation tools and standardized benchmark suites, particularly within platforms like gem5. This work introduces a parameterizable RISC-V Vector Architecture model by

By Admin 29 Oct 2021 • 2 min read •

Research

Vortex: Extending the RISC-V ISA for GPGPU and 3D-GraphicsResearch

Abstract Vortex introduces a minimally intrusive ISA extension to the RISC-V instruction set architecture, specifically designed to facilitate GPGPU and 3D-graphics research and address the scarcity of open-source GPU infrastructure. The design is

By Admin 21 Oct 2021 • 2 min read •

Research

Vega: A 10-Core SoC for IoT End-Nodes with DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode

Abstract Vega is a 10-core RISC-V System-on-Chip designed specifically for ultra-low-power IoT end-nodes requiring complex near-sensor analytics and high performance. It features a novel MRAM-based state-retentive cognitive sleep mode that consumes only 1.

By Admin 18 Oct 2021 • 2 min read •

Research

The Accuracy and Efficiency of Posit Arithmetic

Abstract This paper evaluates the accuracy and efficiency of posit arithmetic against traditional IEEE 754 FP32 by implementing a custom Posit Arithmetic Unit (POSAR) integrated into a RISC-V Rocket Chip core. While 32-bit

By Admin 16 Sep 2021 • 2 min read •

Research

Nvidia CUDA software ported to open source RISC-V GPGPU project #RISCV #CUDA @TomsHardware - Adafruit

Abstract Nvidia's proprietary CUDA parallel computing platform has been successfully ported to an open-source RISC-V General-Purpose GPU (GPGPU) project. This achievement addresses a critical software compatibility barrier, allowing code developed for

By Admin 8 Sep 2021 • 2 min read •

Research

End-to-end 100-TOPS/W Inference With Analog In-Memory Computing: Are We There Yet?

Abstract This paper addresses the integration challenges of Analog In-Memory Acceleration (IMA) within digital systems by proposing a heterogeneous architecture coupling 8 RISC-V cores with an IMA in a shared-memory cluster. Analysis of

By Admin 3 Sep 2021 • 2 min read •

Research

A Novel Compaction Approach for SBST Test Programs

Abstract This work introduces a novel compaction strategy designed to significantly reduce the size and duration of Self-Test Library (STL) programs used for in-field testing of safety-critical processors. The approach analyzes the interaction

By Admin 2 Sep 2021 • 2 min read •