Research

Fast Selective Flushing to Mitigate Contention-based Cache Timing Attacks

Abstract This paper introduces Fast Selective Flushing (FaSe), a novel hardware/software countermeasure designed to mitigate contention-based cache timing attacks efficiently. FaSe utilizes a RISC-V ISA extension (one flush instruction) and minimal cache

By Admin 12 Apr 2022 • 2 min read •

Research

Leverage the Average: Averaged Sampling in Pre-Silicon Side-Channel Leakage Assessment

Abstract This paper introduces Averaged Sampling, a novel technique to significantly reduce the power simulation cost associated with pre-silicon side-channel leakage assessment. By downsampling and averaging high-resolution power traces, the methodology drastically cuts

By Admin 8 Apr 2022 • 2 min read •

Research

Systematic Prevention of On-Core Timing Channels by Full Temporal Partitioning

Abstract This work addresses microarchitectural timing channels by proposing a systematic hardware defense mechanism based on full temporal partitioning. Leveraging the RISC-V ISA, the authors introduce a new temporal fence instruction, fence.t,

By Admin 24 Feb 2022 • 2 min read •

Research

RISC-V AI Chips Will Be Everywhere - IEEE Spectrum

Abstract RISC-V architecture is rapidly emerging as the foundation for next-generation AI accelerators, promising ubiquity across diverse computing domains. This proliferation is driven by RISC-V's intrinsic flexibility, allowing developers to implement

By Admin 24 Feb 2022 • 2 min read •

Research

CVA6's Data cache: Structure and Behavior

Abstract This paper addresses the critical lack of detailed documentation regarding the data cache microarchitecture within the widely used RISC-V CVA6 core, a necessary precursor for successful security research. Since microarchitectural attacks like

By Admin 8 Feb 2022 • 1 min read •

Research

CVA6's Data cache: Structure and Behavior

Originally published on ArXiv - Hardware Architecture Computer Science > Cryptography and Security arXiv:2202.03749v3 (cs) [Submitted on 8 Feb 2022 (v1), last revised 5 Jul 2022 (this version, v3)] Title:CVA6&

By Admin 8 Feb 2022 • 5 min read •

Research

Do You Know For Sure Your RISC-V RTL Doesn’t Contain Any Surprises? - Semiconductor Engineering

Abstract The article critically examines the challenges associated with rigorous verification and validation of RISC-V Register Transfer Level (RTL) designs. It highlights the potential for hidden bugs, security vulnerabilities, or unintended features—termed

By Admin 3 Feb 2022 • 2 min read •

Research

DuVisor: a User-level Hypervisor Through Delegated Virtualization

Abstract DuVisor introduces the concept of "delegated virtualization" to fundamentally redesign hypervisor architecture, achieving a purely user-level hypervisor by separating the control plane from the data plane. This design allows DuVisor

By Admin 24 Jan 2022 • 2 min read •

Research

Dustin: A 16-Cores Parallel Ultra-Low-Power Cluster with 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode

Abstract Dustin is a 16-core parallel ultra-low-power RISC-V cluster designed for edge devices, focusing on energy-intensive Deep Neural Network (DNN) workloads. Its key innovation is the support for fully flexible 2- to 32-bit

By Admin 21 Jan 2022 • 2 min read •

Research

HEROv2: Full-Stack Open-Source Research Platform for Heterogeneous Computing

Abstract HEROv2 is an FPGA-based, full-stack, open-source research platform designed to enable fast and accurate exploration of heterogeneous computing architectures, circumventing the compromises of traditional simulators. It integrates application-class 64-bit hosts (ARMv8 or

By Admin 11 Jan 2022 • 2 min read •

Research

A Heterogeneous In-Memory Computing Cluster For Flexible End-to-End Inference of Real-World Deep Neural Networks

Abstract This paper presents a heterogeneous, tightly-coupled clustered architecture integrating 8 RISC-V cores, an analog In-Memory Computing (IMC) accelerator, and digital accelerators, designed for flexible end-to-end deep neural network (DNN) inference in TinyML

By Admin 4 Jan 2022 • 2 min read •

Research

A Parallel SystemC Virtual Platform for Neuromorphic Architectures

Abstract Simulating complex neuromorphic architectures and benchmarking demanding Artificial Neural Network (ANN) applications requires significant computational resources during the early design phase. This paper presents a novel parallel SystemC-based Virtual Platform (VP) specifically

By Admin 24 Dec 2021 • 1 min read •