Research

MiniFloat-NN and ExSdotp: An ISA Extension and a Modular Open Hardware Unit for Low-Precision Training on RISC-V cores

Abstract This paper introduces MiniFloat-NN, a RISC-V Instruction Set Architecture (ISA) extension, and ExSdotp, a modular open hardware unit, designed to accelerate low-precision neural network training using 8-bit and 16-bit floating-point formats. The

By Admin 7 Jul 2022 • 2 min read •

Research

Experimental evaluation of neutron-induced errors on a multicore RISC-V platform

Abstract This study experimentally evaluates neutron-induced soft errors on the GAP8 multicore RISC-V ASIC platform, addressing the need for reliability data in safety-critical domains. The research found that computing-intensive applications, specifically Convolutional Neural

By Admin 17 Jun 2022 • 2 min read •

Research

CuPBoP: CUDA for Parallelized and Broad-range Processors

Abstract CuPBoP (CUDA for Parallelized and Broad-range Processors) is a novel framework designed to execute proprietary CUDA code on non-NVIDIA hardware, addressing the limitations of vendor lock-in and enabling data-parallel computing in heterogeneous

By Admin 16 Jun 2022 • 2 min read •

Research

Muntjac -- Open Source Multicore RV64 Linux-capable SoC

Abstract Muntjac is an open-source collection of components utilized to construct a multicore, Linux-capable System-on-Chip (SoC). This design incorporates a 64-bit RISC-V core and a cache subsystem, leveraging the TileLink interconnect to achieve

By Admin 14 Jun 2022 • 1 min read •

Research

Enabling Heterogeneous, Multicore SoC Research with RISC-V and ESP

Abstract This paper addresses the scarcity of open-source SoC platforms capable of integrating the growing number of open-source RISC-V processors for heterogeneous designs. The authors present modifications to ESP, an open-source SoC platform,

By Admin 4 Jun 2022 • 1 min read •

Research

Scale up your In-Memory Accelerator: Leveraging Wireless-on-Chip Communication for AIMC-based CNN Inference

Abstract Analog In-Memory Computing (AIMC) scalability is limited by the massive bandwidth and low latency required for on-chip communication, which traditional infrastructure cannot support. This work introduces a many-tile AIMC architecture that resolves

By Admin 3 Jun 2022 • 2 min read •

Research

PiDRAM: An FPGA-based Framework for End-to-end Evaluation of Processing-in-DRAM Techniques

Abstract PiDRAM is the first flexible, end-to-end, and open-source FPGA-based framework enabling the evaluation of real Processing-in-DRAM (PiM) techniques using real DRAM chips. The framework is prototyped on a Xilinx ZC706 FPGA, integrated

By Admin 1 Jun 2022 • 2 min read •

Research

On the Simulation of Hypervisor Instructions for Accurate Timing Simulation of Virtualized Systems

Abstract Traditional full-system simulators for virtualized environments often abstract hypercalls, causing inaccurate timing results. This paper introduces a novel simulation approach that explicitly executes hypervisor instructions alongside OS and application code. This methodology,

By Admin 1 Jun 2022 • 1 min read •

Research

On-Demand Redundancy Grouping: Selectable Soft-Error Tolerance for a Multicore Cluster

Abstract This paper introduces On-Demand Redundancy Grouping (ODRG), a novel architectural scheme that provides selectable soft-error tolerance for multicore clusters operating in critical or hostile environments. Implemented on a six-core open-source RISC-V cluster,

By Admin 25 May 2022 • 2 min read •

Research

Design and Implementation of a Secure RISC-V Microprocessor

Abstract The authors detail the design of a secure, bit-serial RISC-V microprocessor that mitigates side-channel attacks using automated, ubiquitous Boolean masking, ensuring all data remains protected without resorting to manual software countermeasures. This

By Admin 10 May 2022 • 2 min read •

Research

Monte Cimone: Paving the Road for the First Generation of RISC-V High-Performance Computers

Abstract Monte Cimone is a fully-operational, multi-blade computer prototype designed as a hardware-software test-bed to explore the challenges of integrating RISC-V into High-Performance Computing (HPC) environments. Utilizing the 64-bit U740 multi-core SoC, the

By Admin 7 May 2022 • 2 min read •

Research

RedMulE: A Compact FP16 Matrix-Multiplication Accelerator for Adaptive Deep Learning on RISC-V-Based Ultra-Low-Power SoCs

Abstract RedMulE is a compact, parametric FP16 matrix-multiplication accelerator designed to enable online finetuning and adaptation of Deep Learning models on ultra-low-power RISC-V-based SoCs. Integrating tightly within a PULP cluster, this engine addresses

By Admin 24 Apr 2022 • 2 min read •