Research

China's Semiconductor Industry: the Promises of RISC-V Open Source Architecture - Institut Montaigne

Originally published on Google News - RISC-V Research China's Semiconductor Industry: the Promises of RISC-V Open Source Architecture  Institut Montaigne AI Analysis Key Highlights * Geopolitical Strategy: China views RISC-V as a

By Admin 9 Sep 2022 • 1 min read •

Research

ProcessorFuzz: Guiding Processor Fuzzing using Control and Status Registers

Abstract ProcessorFuzz is a novel hardware fuzzer designed for efficient verification of complex processor Register-Transfer Level (RTL) designs. It introduces a CSR-transition coverage metric that guides the fuzzing process by monitoring Control and

By Admin 5 Sep 2022 • 2 min read •

Research

Soft Tiles: Capturing Physical Implementation Flexibility for Tightly-Coupled Parallel Processing Clusters

Abstract This paper introduces the concept of "Soft Tiles" to capture and exploit physical implementation flexibility within tightly-coupled processing clusters used in modern high-performance architectures. The research explores how varying the

By Admin 2 Sep 2022 • 2 min read •

Research

Technical Paper Round-Up: Aug 23 - Semiconductor Engineering

Originally published on Google News - RISC-V Research Technical Paper Round-Up: Aug 23  Semiconductor Engineering

By Admin 23 Aug 2022 •

Research

Kraken: A Direct Event/Frame-Based Multi-sensor Fusion SoC for Ultra-Efficient Visual Processing in Nano-UAVs

Abstract Kraken is an ultra-low-power, heterogeneous System-on-Chip (SoC) fabricated in 22nm FDX technology designed to enable complex, autonomous visual tasks for Nano-UAVs under tight power constraints. The chip achieves high-speed, multi-functional visual processing

By Admin 18 Aug 2022 • 2 min read •

Research

Implementing Cryptographic Algorithms for the RISC-V Instruction Set Architecture in Two Cases - Semiconductor Engineering

Abstract The analyzed work details the successful implementation and evaluation of core cryptographic algorithms tailored for the RISC-V Instruction Set Architecture. The research specifically contrasts performance and complexity across 'Two Cases,'

By Admin 18 Aug 2022 • 2 min read •

Research

SiFive Is Leading The Way For Innovation On RISC-V - Forbes

Abstract The article highlights SiFive's pivotal role in spearheading innovation within the RISC-V ecosystem, transforming the open instruction set architecture into a commercially viable, high-performance solution. SiFive is driving RISC-V adoption

By Admin 8 Aug 2022 • 2 min read •

Research

An Enclave-based TEE for SE-in-SoC in RISC-V Industry

Abstract This work introduces an Enclave-based Trusted Execution Environment (TEE) designed to secure integrated Secure Elements (SE) within RISC-V Systems-on-Chip (SoC). Addressing the rising complexity and security flaws of traditional SE-in-SoC designs, the

By Admin 7 Aug 2022 • 2 min read •

Research

Static Hardware Partitioning on RISC-V -- Shortcomings, Limitations, and Prospects

Abstract This paper investigates the viability of static hardware partitioning (SHP) on multi-core RISC-V processors essential for consolidating mixed-criticality and real-time embedded workloads while ensuring freedom from interference. The authors identify significant shortcomings

By Admin 4 Aug 2022 • 2 min read •

Research

RTL to GDS-II flow Archives - Semiconductor Engineering

Abstract The featured archive extensively covers the complete semiconductor physical design pipeline, detailing the critical conversion process from Register-Transfer Level (RTL) descriptions to the final manufacturing data format, GDS-II. It explores the methodologies

By Admin 21 Jul 2022 • 2 min read •

Research

Spatz: A Compact Vector Processing Unit for High-Performance and Energy-Efficient Shared-L1 Clusters

Abstract Spatz is a novel, compact 32-bit vector processing unit designed as an energy-efficient Processing Element for large-scale clusters leveraging shared L1 memory, specifically targeting mitigation of the Von Neumann Bottleneck. Built upon

By Admin 16 Jul 2022 • 2 min read •

Research

ERIC: An Efficient and Practical Software Obfuscation Framework

Abstract ERIC is an efficient and general software obfuscation framework designed to protect distributed software executables against both static and dynamic analysis. It leverages Physical Unclonable Functions (PUFs) to generate unique device identifiers

By Admin 15 Jul 2022 • 2 min read •