Research

HULK-V: a Heterogeneous Ultra-low-power Linux capable RISC-V SoC

Abstract HULK-V is an open-source, ultra-low-power, heterogeneous RISC-V System-on-Chip designed to bring full Linux capability and agility to energy-constrained IoT applications. It combines a 64-bit RISC-V processor with an 8-core Programmable Multi-Core Accelerator

By Admin 27 Nov 2022 • 2 min read •

Research

AXI-Pack: Near-Memory Bus Packing for Bandwidth-Efficient Irregular Workloads

Abstract AXI-Pack is proposed as an extension to the ARM AXI4 protocol designed to address the bandwidth inefficiencies of irregular memory streams (strided and indirect accesses) in on-chip interconnects. This extension introduces specialized

By Admin 18 Nov 2022 • 2 min read •

Research

Trusted Hart for Mobile RISC-V Security

Abstract This paper addresses the critical need for a robust Trusted Execution Environment (TEE) within future RISC-V mobile devices, contrasting with the established Arm security architecture. The authors propose a novel security architecture

By Admin 18 Nov 2022 • 2 min read •

Research

RISC-V Is Far from Being an Alternative to x86 and Arm in HPC - HPCwire

Abstract This article critically assesses the current state of RISC-V adoption in High-Performance Computing (HPC), concluding that the open-source ISA remains significantly behind established architectures like x86 and Arm. The primary barriers to

By Admin 18 Nov 2022 • 2 min read •

Research

The BlackParrot BedRock Cache Coherence System

Abstract This paper presents BP-BedRock, an open-source, directory-based MOESIF cache coherence system implemented within the BlackParrot 64-bit RISC-V multicore processor. The system notably includes both a fixed-function FSM and a microcode programmable coherence

By Admin 11 Nov 2022 • 2 min read •

Research

Microprocessor Design with Dynamic Clock Source and Multi-Width Instructions

Abstract This paper introduces the design of a novel 32-bit microprocessor based on the RISC-V Instruction Set Architecture. The key innovation is the utilization of a dynamic clock source, which significantly enhances efficiency

By Admin 8 Nov 2022 • 1 min read •

Research

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Abstract This paper presents the first open-source implementation of the recently finalized RISC-V V 1.0 Vector extension, titled "New Ara," providing essential insights into the resulting micro-architecture and design choices.

By Admin 17 Oct 2022 • 2 min read •

Research

End-to-End QoS for the Open Source Safety-Relevant RISC-V SELENE Platform

Abstract This paper details an end-to-end Quality of Service (QoS) approach for the SELENE platform, a high-performance RISC-V based heterogeneous SoC targeting safety-related real-time systems. The goal is to provide robust performance guarantees

By Admin 10 Oct 2022 • 1 min read •

Research

SafeSoftDR: A Library to Enable Software-based Diverse Redundancy for Safety-Critical Tasks

Abstract Microcontrollers often lack native hardware support for lockstepped execution, crucial for achieving the highest safety integrity levels and mitigating common cause failures. SafeSoftDR is a new library designed to enable software-based diverse

By Admin 3 Oct 2022 • 2 min read •

Research

RISC-V Toolchain and Agile Development based Open-source Neuromorphic Processor

Abstract This paper introduces Wenquxing 22A, a novel, low-power, open-source neuromorphic processor designed to accelerate Spiking Neural Networks (SNNs). It solves the energy inefficiency of traditional CPU-accelerator architectures by integrating the SNN calculation

By Admin 2 Oct 2022 • 2 min read •

Research

Evaluating the effects of reducing voltage margins for energy-efficient operation of MPSoCs

Abstract This letter assesses the energy efficiency gains available by aggressively reducing voltage guardbands on a commercial RISC-V Multi-Processor System-on-Chip (MPSoC). Standard voltage margins ensure reliability but severely limit energy efficiency, a critical

By Admin 25 Sep 2022 • 2 min read •

Research

China's Semiconductor Industry: the Promises of RISC-V Open Source Architecture - Institut Montaigne

Abstract The article analyzes China's strategic shift toward adopting the open-source RISC-V architecture as a critical path to semiconductor self-sufficiency. This move aims to bypass reliance on proprietary foreign Intellectual Property

By Admin 9 Sep 2022 • 1 min read •