Research

RISE: RISC-V SoC for En/decryption Acceleration on the Edge for Homomorphic Encryption

Abstract RISE is a novel RISC-V System-on-Chip (SoC) designed to accelerate critical message-to-ciphertext conversion operations for Homomorphic Encryption (HE) on resource-constrained edge devices. The architecture overcomes bottlenecks in error sampling and Number Theoretic

By Admin 14 Feb 2023 • 2 min read •

Research

Quark: An Integer RISC-V Vector Processor for Sub-Byte Quantized DNN Inference

Abstract Quark is an integer RISC-V vector processor specifically tailored for highly efficient sub-byte quantized Deep Neural Network (DNN) inference. Built upon the open-source Ara processor, Quark achieves significant area and power savings

By Admin 12 Feb 2023 • 2 min read •

Research

Is RISC-V Ready For Supercomputing? - Semiconductor Engineering

Abstract The article evaluates the readiness of the open-source RISC-V architecture to meet the rigorous demands of High-Performance Computing (HPC) and supercomputing environments. While RISC-V offers key advantages like customization and potential power

By Admin 9 Feb 2023 • 2 min read •

Research

Adding Explicit Load-Acquire and Store-Release Instructions to the RISC-V ISA

Abstract This paper proposes the addition of explicit load-acquire and store-release instructions to the RISC-V ISA, a crucial step for managing synchronization in architectures utilizing weak memory models. The authors demonstrate support by

By Admin 7 Feb 2023 • 2 min read •

Research

CVA6 RISC-V Virtualization: Architecture, Microarchitecture, and Design Space Exploration

Abstract This article describes the implementation and optimization of hardware virtualization support for the open-source RISC-V CVA6 core, encompassing architecture and microarchitecture enhancements. The authors introduce specific structures like the G-Stage TLB (GTLB)

By Admin 6 Feb 2023 • 2 min read •

Research

RedMule: A Mixed-Precision Matrix-Matrix Operation Engine for Flexible and Energy-Efficient On-Chip Linear Algebra and TinyML Training Acceleration

Abstract RedMulE is a specialized, mixed-precision matrix multiplication engine designed to enable energy-efficient TinyML training, which traditionally requires costly floating-point operations. Integrated into a RISC-V PULP cluster, the engine supports FP16 and hybrid

By Admin 10 Jan 2023 • 2 min read •

Research

TinyVers: A Tiny Versatile System-on-chip with State-Retentive eMRAM for ML Inference at the Extreme Edge

Abstract TinyVers is an ultra-low power, versatile System-on-Chip designed for Machine Learning inference at the Extreme Edge, integrating a RISC-V host processor and a dataflow reconfigurable ML accelerator. The SoC leverages state-retentive embedded

By Admin 9 Jan 2023 • 2 min read •

Research

How Secure Are RISC-V Chips? - Semiconductor Engineering

Abstract The security of RISC-V chips is highly dependent on implementation quality and specific architecture extensions rather than being monolithic, posing unique verification and trust challenges due to its open and customizable nature.

By Admin 5 Jan 2023 • 2 min read •

Research

BARVINN: Arbitrary Precision DNN Accelerator Controlled by a RISC-V CPU

Abstract BARVINN is an open-source DNN accelerator that enables deep learning inference at arbitrary precision using dedicated, bit-level configurable Processing Elements (PEs). The system is efficiently managed by a dedicated RISC-V CPU controller,

By Admin 31 Dec 2022 • 2 min read •

Research

RISC-V decoupled Vector Processing Unit (VPU) For HPC - Semiconductor Engineering

Abstract The article details a new RISC-V decoupled Vector Processing Unit (VPU) specifically designed to meet the rigorous demands of High-Performance Computing (HPC) applications. This architectural separation enhances throughput and improves latency tolerance

By Admin 20 Dec 2022 • 2 min read •

Research

Generic Tagging for RISC-V Binaries

Abstract The paper introduces COGENT, a generic instruction tag generator designed for RISC-V binaries to simplify the implementation of custom hardware security solutions without requiring specialized compilers. COGENT associates configurable tags (1 to

By Admin 11 Dec 2022 • 2 min read •

Research

TCN-CUTIE: A 1036 TOp/s/W, 2.72 uJ/Inference, 12.2 mW All-Digital Ternary Accelerator in 22 nm FDX Technology

Abstract TCN-CUTIE is a novel, all-digital ternary neural network accelerator implemented in 22 nm FDX technology and integrated into a RISC-V SoC, designed specifically for stringent TinyML constraints. It achieves a record peak

By Admin 1 Dec 2022 • 2 min read •