Research

NEUROPULS: NEUROmorphic energy-efficient secure accelerators based on Phase change materials aUgmented siLicon photonicS

Abstract The Horizon Europe NEUROPULS project introduces novel secure and energy-efficient neuromorphic accelerators leveraging Phase Change Material (PCM) augmented silicon photonics technology. These accelerators are designed to interface seamlessly with RISC-V architectures via

By Admin 4 May 2023 • 2 min read •

Research

NPS: A Framework for Accurate Program Sampling Using Graph Neural Network

Abstract Neural Program Sampling (NPS) is a novel framework that utilizes a Graph Neural Network (GNN) approach to accurately select representative simulation points, addressing the limitations and time-consuming manual tuning required by traditional

By Admin 18 Apr 2023 • 2 min read •

Research

CoVE: Towards Confidential Computing on RISC-V Platforms

Abstract This paper introduces CoVE, a proposed reference architecture for implementing Confidential Computing on RISC-V platforms. It addresses the vulnerability of large Trusted Computing Bases (TCBs) in traditional multi-tenant environments by defining hardware-attested

By Admin 12 Apr 2023 • 1 min read •

Research

Programming Language Assisted Waveform Analysis: A Case Study on the Instruction Performance of SERV

Abstract This paper addresses the difficulty of fine-grained RISC-V core analysis in a rapidly expanding ecosystem by proposing a programming language-assisted methodology. The innovation utilizes WAWK, a front-end for the Waveform Analysis Language,

By Admin 12 Apr 2023 • 2 min read •

Research

Optimized Real-Time Assembly in a RISC Simulator

Abstract This article introduces the Assembly/Simulation Platform for Illustration of RISC-V in Education (ASPIRE), an integrated tool designed to teach RISC-V ISA and CPU architecture concepts. The authors evaluate two assembly algorithms

By Admin 6 Apr 2023 • 2 min read •

Research

Tensor Slicing and Optimization for Multicore NPUs

Abstract This paper introduces the Tensor Slicing Optimization (TSO) pass for the TensorFlow XLA/LLVM compiler, designed to improve CNN performance on highly constrained Multicore Neural Processor Units (NPUs). TSO efficiently partitions convolution

By Admin 6 Apr 2023 • 2 min read •

Research

DARKSIDE: A Heterogeneous RISC-V Compute Cluster for Extreme-Edge On-Chip DNN Inference and Training

Abstract DARKSIDE is a System-on-Chip featuring a heterogeneous cluster of eight RISC-V cores designed for extreme-edge (TinyML) DNN inference and training, integrating 2-bit to 32-bit mixed-precision integer capabilities. To boost performance, the cluster

By Admin 31 Mar 2023 • 2 min read •

Research

Simulation Environment with Customized RISC-V Instructions for Logic-in-Memory Architectures

Abstract Addressing the challenges of the memory wall, this work proposes using customized RISC-V instructions to support Logic-in-Memory (LiM) operations within computing architectures. The key innovation is a modular, cycle-accurate simulation environment developed

By Admin 21 Mar 2023 • 2 min read •

Research

Hybrid Modular Redundancy: Exploring Modular Redundancy Approaches in RISC-V Multi-Core Computing Clusters for Reliable Processing in Space

Abstract This paper presents Hybrid Modular Redundancy (HMR), a novel fault-tolerance scheme designed for RISC-V multi-core computing clusters intended for space applications. HMR enables flexible, on-demand dual-core or triple-core lockstep grouping with runtime

By Admin 15 Mar 2023 • 2 min read •

Research

SwRI Is Researching ARM, RISC-V Processors For Use As Faster Spaceflight Computers - SpaceRef

Abstract Southwest Research Institute (SwRI) is actively researching and evaluating modern processor architectures, specifically ARM and RISC-V, for future use in spaceflight computing systems. This effort aims to overcome the severe performance limitations

By Admin 28 Feb 2023 • 2 min read •

Research

ProSpeCT: Provably Secure Speculation for the Constant-Time Policy (Extended version)

Abstract ProSpeCT is a generic formal processor model designed to provide provably secure speculative execution specifically for programs adhering to the constant-time policy. It guarantees security by tracking secret data within the pipeline

By Admin 23 Feb 2023 • 2 min read •

Research

ColibriES: A Milliwatts RISC-V Based Embedded System Leveraging Neuromorphic and Neural Networks Hardware Accelerators for Low-Latency Closed-loop Control Applications

Abstract ColibriES is a novel milliwatt RISC-V based embedded system featuring the first-ever dedicated event-sensor interfaces and full neuromorphic processing pipelines. Built upon the Kraken System-on-Chip (SoC), it integrates a heterogeneous PULP processor

By Admin 15 Feb 2023 • 2 min read •