Research

Chinese Research Team Uses AI to Design a Processor in 5 Hours - TechPowerUp

Abstract A Chinese research team achieved a significant breakthrough by successfully designing a functional processor core using artificial intelligence tools. This innovative approach dramatically compressed the complex chip design lifecycle, completing the entire

By Admin 30 Jun 2023 • 2 min read •

Research

A Survey on Deep Learning Hardware Accelerators for Heterogeneous HPC Platforms

Abstract This comprehensive survey categorizes the recent evolution of Deep Learning (DL) hardware accelerators essential for fulfilling the demanding performance requirements of High-Performance Computing (HPC) applications. It thoroughly reviews established platforms, including GPUs,

By Admin 27 Jun 2023 • 2 min read •

Research

Pushing the Limits of Machine Design: Automated CPU Design with AI

Abstract This paper presents a novel AI approach that autonomously designs an industrial-scale Central Processing Unit (CPU) solely from external input-output observations, navigating an unprecedented search space of $10^{10^{540}}$. Using a

By Admin 21 Jun 2023 • 2 min read •

Research

Sparq: A Custom RISC-V Vector Processor for Efficient Sub-Byte Quantized Inference

Abstract Sparq is a custom RISC-V vector processor designed specifically to accelerate highly efficient sub-byte Quantized Neural Network (QNN) inference. This architecture modifies the open-source Ara core by removing the Floating-Point Unit and

By Admin 16 Jun 2023 • 2 min read •

Research

ControlPULP: A RISC-V On-Chip Parallel Power Controller for Many-Core HPC Processors with FPGA-Based Hardware-In-The-Loop Power and Thermal Emulation

Abstract ControlPULP is an open-source, HW/SW RISC-V parallel Power Controller System (PCS) designed to manage complex, real-time closed-loop power and thermal requirements in many-core HPC processors. The architecture utilizes a single-core MCU

By Admin 15 Jun 2023 • 2 min read •

Research

ColibriUAV: An Ultra-Fast, Energy-Efficient Neuromorphic Edge Processing UAV-Platform with Event-Based and Frame-Based Cameras

Abstract ColibriUAV is an ultra-fast, energy-efficient UAV platform that combines traditional frame-based cameras with dynamic vision sensors (DVS) for robust, low-latency perception. The system is centered around Kraken, a novel low-power RISC-V System

By Admin 27 May 2023 • 2 min read •

Research

A Classical Architecture For Digital Quantum Computers

Abstract This paper presents a scalable classical control architecture for digital quantum computers, tackling major scaling bottlenecks by integrating a multi-core RISC-V CPU with in-house control electronics. The architecture features parallel quantum operation

By Admin 23 May 2023 • 2 min read •

Research

Marsellus: A Heterogeneous RISC-V AI-IoT End-Node SoC with 2-to-8b DNN Acceleration and 30%-Boost Adaptive Body Biasing

Abstract Marsellus is a heterogeneous RISC-V System-on-a-Chip designed for low-power AI-IoT end-nodes fabricated in GlobalFoundries 22nm FDX. The SoC combines a cluster of 16 RISC-V DSP cores supporting specialized 2-to-4b arithmetic (XpulpNN) with

By Admin 15 May 2023 • 2 min read •

Research

Echoes: a 200 GOPS/W Frequency Domain SoC with FFT Processor and I2S DSP for Flexible Data Acquisition from Microphone Arrays

Abstract ECHOES is a novel System-On-a-Chip designed for ultra-low-power, high-performance frequency domain processing required in demanding IoT applications like audio and radar. It integrates a specialized RISC-V core with DSP extensions and a

By Admin 12 May 2023 • 2 min read •

Research

Big-PERCIVAL: Exploring the Native Use of 64-Bit Posit Arithmetic in Scientific Computing

Abstract This work, titled "Big-PERCIVAL," explores the native implementation and use of 64-bit posit arithmetic (posit64) and associated quire operations by extending the PERCIVAL RISC-V core and Xposit custom ISA. Results

By Admin 11 May 2023 • 2 min read •

Research

Sparse Stream Semantic Registers: A Lightweight ISA Extension Accelerating General Sparse Linear Algebra

Abstract This paper introduces Sparse Stream Semantic Registers (SSSR), a lightweight ISA extension for RISC-V designed to accelerate general sparse linear algebra by efficiently handling both one- and two-sided operand sparsity. SSSR accelerates

By Admin 9 May 2023 • 2 min read •

Research

Cheshire: A Lightweight, Linux-Capable RISC-V Host Platform for Domain-Specific Accelerator Plug-In

Abstract Cheshire is a lightweight, Linux-capable 64-bit RISC-V host platform designed to facilitate the seamless integration of domain-specific accelerators, targeting energy-constrained IoT and TinyML applications. Its core architectural features include a unique low-pin-count

By Admin 8 May 2023 • 2 min read •