Research

A RISC-V MCU with adaptive reverse body bias and ultra-low-power retention mode in 22 nm FD-SOI

Abstract This paper introduces a highly energy-efficient 32-bit RISC-V MCU fabricated in 22 nm FD-SOI technology, utilizing adaptive reverse body biasing (RBB) to achieve ultra-low leakage current across the full industrial temperature range.

By Admin 13 Oct 2023 • 2 min read •

Research

Trikarenos: A Fault-Tolerant RISC-V-based Microcontroller for CubeSats in 28nm

Abstract Trikarenos is a fault-tolerant, 32-bit RISC-V microcontroller SoC fabricated in an advanced TSMC 28nm technology, specifically designed to mitigate radiation-induced Single Event Upsets (SEUs) in harsh space environments like CubeSats. Its key

By Admin 3 Oct 2023 • 2 min read •

Research

Spatz: Clustering Compact RISC-V-Based Vector Units to Maximize Computing Efficiency

Abstract Spatz is a novel, compact 64-bit floating-point RISC-V vector processor utilizing the Zve64d extension, designed to maximize computing efficiency in clustered architectures. The architecture achieves peak energy efficiency by employing a highly

By Admin 18 Sep 2023 • 2 min read •

Research

Using LLMs to Facilitate Formal Verification of RTL

Abstract To mitigate the burden of writing SystemVerilog Assertions (SVA) for Formal Property Verification (FPV), this study explores using LLMs like GPT-4 to automatically generate verification properties directly from RTL code. Researchers designed

By Admin 18 Sep 2023 • 2 min read •

Research

A Precision-Scalable RISC-V DNN Processor with On-Device Learning Capability at the Extreme Edge

Abstract This paper presents a precision-scalable RISC-V DNN processor designed for extreme edge devices, tackling the challenges of efficient inference and enabling on-device learning. The architecture supports diverse fixed-point inference precisions ranging from

By Admin 15 Sep 2023 • 2 min read •

Research

Short reasons for long vectors in HPC CPUs: a study based on RISC-V

Abstract This study analyzes the performance benefits of exceptionally long vector units in High-Performance Computing (HPC) CPUs using a customizable RISC-V core setup. Testing vector lengths up to 256 double-precision elements against non-dense

By Admin 13 Sep 2023 • 1 min read •

Research

SG2042 64-Core RISC-V CPU Versus Existing RISC-V HW And High Performance x86 CPUs - Semiconductor Engineering

Abstract The technical analysis focuses on the SG2042, a monumental 64-core CPU built upon the RISC-V instruction set architecture, representing a critical push into high-performance computing (HPC) markets. The study rigorously compares the

By Admin 13 Sep 2023 • 2 min read •

Research

Compressed Real Numbers for AI: a case-study using a RISC-V CPU

Abstract This paper investigates optimizing Deep Neural Network (DNN) inference on CPUs by utilizing compressed number formats like bfloat and posit to reduce memory bandwidth demands. The core innovation is proposing a method

By Admin 11 Sep 2023 • 2 min read •

Research

Octopus: A Heterogeneous In-network Computing Accelerator Enabling Deep Learning for network

Abstract The Octopus accelerator addresses the challenge of deploying Deep Learning (DL) models directly onto programmable in-network computing devices, which typically lack the necessary processing power and generality. It employs a heterogeneous architecture

By Admin 22 Aug 2023 • 2 min read •

Research

Unlocking Hardware Security Assurance: The Potential of LLMs

Abstract This paper introduces the Natural Language Processing-based Security Property Generator (NSPG), a novel automated method designed to enhance hardware security assurance in complex System-on-Chips (SoCs). NSPG utilizes HS-BERT, the first language model

By Admin 21 Aug 2023 • 2 min read •

Research

Towards a Formally Verified Security Monitor for VM-based Confidential Computing

Abstract This paper proposes a novel methodology for formally modeling and proving a security monitor for VM-based confidential computing, addressing the lack of verification in existing systems critical for high-assurance applications. It introduces

By Admin 20 Aug 2023 • 2 min read •

Research

Understanding Lasso and Jolt, from theory to code - a16z crypto

Abstract The article analyzes Lasso and Jolt, two recent cryptographic innovations designed to dramatically improve the efficiency of Zero-Knowledge (ZK) proving systems. Lasso introduces a highly optimized lookup argument that minimizes prover overhead

By Admin 10 Aug 2023 • 2 min read •