Research

SentryCore: A RISC-V Co-Processor System for Safe, Real-Time Control Applications

Abstract SentryCore is a reliable, open-source RISC-V co-processor system (mega-IP) designed for advanced, real-time control functions in safety-critical applications like automotive and robotics. It ensures reliability by using three embedded RISC-V cores operating

By Admin 16 May 2024 • 2 min read •

Research

Basilisk: Achieving Competitive Performance with Open EDA Tools on an Open-Source Linux-Capable RISC-V SoC

Abstract The paper introduces Basilisk, an optimized application-specific integrated circuit (ASIC) implementation built upon the open-source Iguana RISC-V SoC, demonstrating a highly effective open-source electronic design automation (EDA) flow. By enhancing synthesis tools

By Admin 6 May 2024 • 2 min read •

Research

PCG: Mitigating Conflict-based Cache Side-channel Attacks with Prefetching

Abstract PCG is a novel prefetching-based scheme designed to effectively mitigate conflict-based cache side-channel attacks without incurring significant performance penalties. It achieves robust security by generating noisy, indistinguishable cache access patterns through a

By Admin 6 May 2024 • 2 min read •

Research

STRELA: STReaming ELAstic CGRA Accelerator for Embedded Systems

Abstract STRELA is an elastic Coarse-Grained Reconfigurable Architecture (CGRA) integrated into an energy-efficient RISC-V System-on-Chip (SoC) designed for the embedded domain. Its microarchitecture specifically supports conditionals and irregular loops, enhancing adaptability for complex,

By Admin 18 Apr 2024 • 2 min read •

Research

Reconfigurable Edge Hardware for Intelligent IDS: Systematic Approach

Abstract This paper addresses the deployment of intelligent Intrusion Detection Systems (I-IDS) on resource-constrained Edge hardware by proposing a systematic approach utilizing reconfigurable FPGA technology. The authors implemented and compared two architectures: a

By Admin 13 Apr 2024 • 2 min read •

Research

Beyond Random Inputs: A Novel ML-Based Hardware Fuzzing

Abstract This paper introduces ChatFuzz, a novel ML-based hardware fuzzer that leverages Large Language Models (LLMs) and Reinforcement Learning (RL) to efficiently generate effective assembly code sequences for processor verification. Utilizing the RISC-V

By Admin 10 Apr 2024 • 2 min read •

Research

Building Jolt: A fast, easy-to-use zkVM - a16z crypto

Abstract a16z crypto has unveiled Jolt, a novel Zero-Knowledge Virtual Machine (zkVM) designed to offer significantly faster proof generation and enhanced ease of use compared to existing solutions. Jolt aims to tackle the

By Admin 9 Apr 2024 • 2 min read •

Research

Huawei is quietly dominating China’s semiconductor supply chain - Mercator Institute for China Studies (MERICS)

Abstract The Mercator Institute for China Studies (MERICS) reports that Huawei is strategically seizing control of China’s domestic semiconductor supply chain, largely circumventing the impact of stringent U.S. sanctions. This dominance

By Admin 9 Apr 2024 • 2 min read •

Research

Design and implementation of a synchronous Hardware Performance Monitor for a RISC-V space-oriented processor

Abstract This paper details the design and implementation of a synchronous Hardware Performance Monitor (HPM), or Performance Measurement Unit (PMU), integrated into a RISC-V processor intended for space-oriented On-Board Computer (OBC) applications. The

By Admin 8 Apr 2024 • 2 min read •

Research

SARIS: Accelerating Stencil Computations on Energy-Efficient RISC-V Compute Clusters with Indirect Stream Registers

Abstract SARIS is a general methodology leveraging register-mapped indirect streams to significantly accelerate performance-critical stencil computations on energy-efficient RISC-V compute clusters. Utilizing this technique on an eight-core system, the authors demonstrate an average

By Admin 8 Apr 2024 • 2 min read •

Research

X-Silicon Unveils Low-Power C-GPU Architecture Combined With RISC-V CPU, Open Standard & Supports Vulkan - Wccftech

Abstract X-Silicon has introduced a novel low-power C-GPU architecture that tightly integrates graphics processing with a RISC-V CPU core. This combined design champions open standards and features native support for the high-performance Vulkan

By Admin 4 Apr 2024 • 1 min read •

Research

QED: Scalable Verification of Hardware Memory Consistency

Abstract QED is a novel, scalable verification methodology designed to detect complex Memory Consistency Model (MCM) bugs in out-of-order (OOO) processors, surpassing the severe scaling limits of prior bounded verification techniques. It achieves

By Admin 3 Apr 2024 • 2 min read •