Research

KWT-Tiny: RISC-V Accelerated, Embedded Keyword Spotting Transformer

Abstract This paper presents KWT-Tiny, an aggressively quantized and retrained Keyword Transformer (KWT) model adapted for bare-metal RISC-V edge devices operating under strict 64kB RAM constraints. Model optimization reduced the size from 2.

By Admin 22 Jul 2024 • 2 min read •

Research

Mixed-precision Neural Networks on RISC-V Cores: ISA extensions for Multi-Pumped Soft SIMD Operations

Abstract This work introduces a novel hardware-software co-design framework featuring specialized Instruction Set Architecture (ISA) extensions and micro-architectural optimizations to efficiently execute mixed-precision neural networks on RISC-V cores. The design includes an expanded

By Admin 19 Jul 2024 • 2 min read •

Research

System-on-Chip (SoC) Market Size, Share, Trends and Growth, 2024-2029 - MarketsandMarkets

Abstract The MarketsandMarkets report forecasts significant compound annual growth for the global System-on-Chip (SoC) market between 2024 and 2029, driven primarily by accelerating digitization and demand across consumer electronics, automotive, and 5G communication

By Admin 11 Jul 2024 • 2 min read •

Research

Trikarenos: Design and Experimental Characterization of a Fault-Tolerant 28nm RISC-V-based SoC

Abstract The Trikarenos design is a fault-tolerant, 28nm RISC-V System-on-Chip developed for demanding automotive and space applications, incorporating Error Correction Codes (ECC) and Triple-Core Lockstep (TCLS) mechanisms. This study experimentally characterizes the fabricated

By Admin 8 Jul 2024 • 2 min read •

Research

Spatzformer: An Efficient Reconfigurable Dual-Core RISC-V V Cluster for Mixed Scalar-Vector Workloads

Abstract Spatzformer is the first reconfigurable dual-core RISC-V V (RVV) cluster designed to overcome the efficiency limitations of multi-core vector processors when facing mixed scalar-vector workloads. It operates in two modes—split mode

By Admin 7 Jul 2024 • 2 min read •

Research

DAC 61: EDA addressing growing system complexity - embedded.com

Abstract The 61st Design Automation Conference (DAC 61) centered on how Electronic Design Automation (EDA) tools are evolving to tackle the exponentially growing complexity of modern electronic systems. Innovations focused heavily on managing

By Admin 3 Jul 2024 • 2 min read •

Research

RISC-V R-Extension: Advancing Efficiency with Rented-Pipeline for Edge DNN Processing

Abstract This paper introduces the RISC-V R-extension, a novel architectural approach designed to enhance Deep Neural Network (DNN) processing efficiency on lightweight edge devices. The R-extension avoids the high power, cost, and area

By Admin 2 Jul 2024 • 2 min read •

Research

AI-PiM—Extending the RISC-V processor with Processing-in-Memory functional units for AI inference at the edge of IoT - Frontiers

Abstract The AI-PiM project introduces a novel extension to the RISC-V processor architecture by integrating specialized Processing-in-Memory (PiM) functional units. This architectural enhancement is specifically designed to accelerate Artificial Intelligence (AI) inference tasks

By Admin 27 Jun 2024 • 2 min read •

Research

NoX: a Compact Open-Source RISC-V Processor for Multi-Processor Systems-on-Chip

Abstract The NoX processor is a compact, open-source, 32-bit RISC-V core designed in System Verilog to serve as a plug-and-play solution for Multi-Processor Systems-on-Chip (MPSoCs) targeting edge computing and IoT applications. It utilizes

By Admin 25 Jun 2024 • 2 min read •

Research

Design, Implementation and Evaluation of the SVNAPOT Extension on a RISC-V Processor

Abstract The paper details the design, implementation, and evaluation of the RISC-V SVNAPOT Extension, intended to reduce Memory Management Unit (MMU) overhead during heavy memory loads. This extension leverages larger 64KB Natural-Power-of-Two (NAPOT)

By Admin 22 Jun 2024 • 2 min read •

Research

Basilisk: An End-to-End Open-Source Linux-Capable RISC-V SoC in 130nm CMOS

Abstract Basilisk is presented as the first end-to-end open-source, Linux-capable RISC-V System-on-Chip (SoC), successfully taped out utilizing IHP's open 130 nm CMOS technology. This achievement validates the capability of open-source hardware

By Admin 21 Jun 2024 • 2 min read •

Research

Occamy: A 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Floating-Point Support in 12nm FinFET

Originally published on ArXiv - Hardware Architecture Abstract We present Occamy, a 432-core RISC-V dual-chiplet 2.5D system for efficient sparse linear algebra and stencil computations on FP64 and narrow (32-, 16-, 8-bit)

By Admin 21 Jun 2024 • 1 min read •