Research

A Flexible Template for Edge Generative AI with High-Accuracy Accelerated Softmax & GELU

Abstract This paper introduces a BFloat16 RISC-V acceleration template for edge Generative AI, specifically addressing the performance bottleneck caused by softmax and GELU non-linearities in Transformer models. The innovation lies in SoftEx, a

By Admin 9 Dec 2024 • 2 min read •

Research

Efficient transformer adaptation for analog in-memory computing via low-rank adapters

Abstract This paper proposes Analog Hardware-Aware Low-Rank Adaptation (AHWA-LoRA) to efficiently adapt large transformer models for Analog In-Memory Computing (AIMC) hardware, circumventing the need for costly full model retraining or analog device reprogramming.

By Admin 26 Nov 2024 • 2 min read •

Research

From CISC to RISC: language-model guided assembly transpilation

Abstract This paper introduces CRT, a lightweight LLM-based assembly transpiler designed to automatically convert x86 (CISC) code to RISC architectures like ARM and RISC-V. This tool addresses the fundamental challenge of migrating legacy

By Admin 25 Nov 2024 • 2 min read •

Research

Teaching Experiences using the RVfpga Package

Abstract The RVfpga course provides a robust, hands-on introduction to computer architecture using the RISC-V instruction set and FPGA technology. This paper details various successful teaching experiences, demonstrating its utility across undergraduate and

By Admin 22 Nov 2024 • 1 min read •

Research

RISC-V Word-Size Modular Instructions for Residue Number Systems

Abstract This article introduces and evaluates specific word-size modular arithmetic instructions designed for the RISC-V Instruction Set Architecture (ISA) to significantly enhance the software implementation of Residue Number Systems (RNS), which are critical

By Admin 21 Nov 2024 • 2 min read •

Research

Advancing Cloud Computing Capabilities on gem5 by Implementing the RISC-V Hypervisor Extension

Abstract This paper presents the successful implementation and rigorous evaluation of the RISC-V H (hypervisor) extension within the gem5 microarchitectural simulator. This integration is crucial for enhancing RISC-V's capabilities in cloud

By Admin 19 Nov 2024 • 1 min read •

Research

White paper on RISC-V market insights - Jon Peddie Research

Abstract Jon Peddie Research released a comprehensive white paper providing critical market insights and forecasts for the rapidly expanding RISC-V ecosystem. The report analyzes the significant competitive advantages derived from the ISA'

By Admin 19 Nov 2024 • 2 min read •

Research

White paper on RISC-V market insights - Jon Peddie

Abstract The "White paper on RISC-V market insights" by Jon Peddie Research delivers a comprehensive analysis and market forecast for the rapidly accelerating adoption of the open-source RISC-V Instruction Set Architecture

By Admin 19 Nov 2024 • 2 min read •

Research

Updates: Past TMT Predictions’ greatest hits and (near) misses - Deloitte

Abstract Deloitte has published an update reviewing the accuracy of its previous Technology, Media, and Telecommunications (TMT) industry predictions. This analysis evaluates the long-term trends identified, distinguishing between successful forecasts (hits) and those

By Admin 19 Nov 2024 • 2 min read •

Research

TreeHouse: An MLIR-based Compilation Flow for Real-Time Tree-based Inference

Abstract TreeHouse presents a novel MLIR-based compilation flow specifically optimized for achieving real-time, low-latency inference of tree-based machine learning models (like Random Forests and GBTs). By leveraging MLIR's retargetability and modular

By Admin 15 Nov 2024 • 2 min read •

Research

OpenGeMM: A High-Utilization GeMM Accelerator Generator with Lightweight RISC-V Control and Tight Memory Coupling

Abstract OpenGeMM is an open-source acceleration platform designed to address the high-utilization challenges of generic RISC-V systems when running DNNs on resource-constrained edge devices. It integrates a parameterized Chisel-coded GeMM core, a lightweight

By Admin 14 Nov 2024 • 2 min read •

Research

Web-Based Simulator of Superscalar RISC-V Processors

Abstract This paper presents an advanced, web-based simulator designed to help students and professionals master the fundamentals of superscalar RISC-V processors, HW/SW co-design, and HPC optimization. The tool features customizable processor and

By Admin 12 Nov 2024 • 1 min read •