Research

Hardware and software build flow with SoCMake

Abstract The increasing complexity of System-on-Chip (SoC) designs requires robust build systems capable of simultaneously managing complex hardware generation and software cross-compilation. Recognizing that existing hardware build systems lack sufficient support for software

By Admin 4 Feb 2025 • 2 min read •

Research

Increasing the Energy-Efficiency of Wearables Using Low-Precision Posit Arithmetic with PHEE

Abstract This paper investigates leveraging low-precision posit arithmetic to significantly enhance the energy efficiency of wearable biomedical devices, focusing on applications like ECG analysis and cough detection. The research confirms that low-bit posit

By Admin 30 Jan 2025 • 2 min read •

Research

Enhanced LPDDR4X PHY in 12 nm FinFET

Abstract This paper presents an enhanced LPDDR4X Physical Layer (PHY) implemented using 12 nm FinFET technology, specifically designed to improve memory reliability and power efficiency. The key innovation is the integration of advanced

By Admin 29 Jan 2025 • 2 min read •

Research

A Tale of Two Sides of Wafer: Physical Implementation and Block-Level PPA on Flip FET with Dual-sided Signals

Abstract This paper presents the Flip FET (FFET), a novel transistor architecture that uses 3D stacking and a fully functional wafer backside to enable dual-sided standard cell designs and signal routing. Utilizing a

By Admin 25 Jan 2025 • 2 min read •

Research

TCDM Burst Access: Breaking the Bandwidth Barrier in Shared-L1 RVV Clusters Beyond 1000 FPUs

Abstract This paper presents the TCDM Burst Access architecture, a software-transparent solution designed to overcome bandwidth limitations in high-core-count RISC-V Vector (RVV) clusters sharing multi-banked L1 memory (TCDM). By employing a Burst Manager

By Admin 24 Jan 2025 • 2 min read •

Research

CIBPU: A Conflict-Invisible Secure Branch Prediction Unit

Abstract Traditional Secure Branch Prediction Units (SBPUs) often suffer from significant performance degradation or weak security due to visible branch conflicts and reliance on vulnerable key update mechanisms. This paper introduces CIBPU, a

By Admin 19 Jan 2025 • 2 min read •

Research

AraXL: A Physically Scalable, Ultra-Wide RISC-V Vector Processor Design for Fast and Efficient Computation on Long Vectors

Abstract AraXL is a novel, ultra-wide RISC-V V vector processor designed to overcome the physical scalability limitations, such as wire dominance, found in state-of-the-art vector designs for HPC and ML applications. It achieves

By Admin 17 Jan 2025 • 2 min read •

Research

Optimizing Structured-Sparse Matrix Multiplication in RISC-V Vector Processors

Abstract This work analyzes and optimizes Structured-Sparse Matrix Multiplication (SSMM) performance for Machine Learning applications running on RISC-V Vector Processors. The authors propose and integrate a new instruction, vindexmac (vector index-multiply-accumulate), designed to

By Admin 17 Jan 2025 • 2 min read •

Research

Multi-Dimensional Vector ISA Extension for Mobile In-Cache Computing

Abstract This paper introduces the Multi-dimensional Vector ISA Extension (MVE) designed specifically for mobile In-Cache Computing (ICC), addressing the inefficiency of existing 1D vector ISAs like RVV when utilizing wide SIMD units. MVE

By Admin 17 Jan 2025 • 2 min read •

Research

Occamy: A 432-Core Dual-Chiplet Dual-HBM2E 768-DP-GFLOP/s RISC-V System for 8-to-64-bit Dense and Sparse Computing in 12nm FinFET

Abstract Occamy is a 432-core, 768-DP-GFLOP/s, dual-chiplet RISC-V system designed specifically to maximize compute efficiency across both dense and sparse FP8-to-FP64 ML and HPC workloads. Utilizing dual-HBM2E memory, a latency-tolerant interconnect, and

By Admin 13 Jan 2025 • 2 min read •

Research

Modern Hardware Security: A Review of Attacks and Countermeasures

Abstract This paper reviews the urgent state of hardware security, driven by the proliferation of cloud, IoT, and smart devices, and the rapid evolution of computing architectures. It provides a comprehensive analysis of

By Admin 8 Jan 2025 • 2 min read •

Research

Mixed-Level Modeling and Evaluation of a Cache-less Grid of Processing Cells

Abstract This article introduces a novel architecture based on a cache-less grid composed of numerous processing cells, designed to maximize parallelism and efficiency for embedded applications. The core innovation lies in utilizing a

By Admin 19 Dec 2024 • 2 min read •