Research

A RISC-V Multicore and GPU SoC Platform with a Qualifiable Software Stack for Safety Critical Systems

Abstract This paper introduces the METASAT platform, a novel RISC-V multicore and GPU System-on-Chip designed as a prototype for future safety-critical space missions. The architecture integrates a space-grade

By Admin 28 Feb 2025 • 1 min read •

Research

Enhancing software-hardware co-design for HEP by low-overhead profiling of single- and multi-threaded programs on diverse architectures with Adaptyst

Abstract The paper introduces Adaptyst, an open-source and architecture-agnostic tool designed to enhance software-hardware co-design for complex applications like High Energy Physics (HEP). Adaptyst provides low-overhead profiling of

By Admin 28 Feb 2025 • 2 min read •

Research

Wildcat: Educational RISC-V Microprocessors

Abstract The paper "Wildcat" challenges the traditional 5-stage pipeline model used in computer architecture education by examining simpler RISC-V organizations for teaching and implementation. Analysis across FPGA and SkyWater130

By Admin 27 Feb 2025 • 2 min read •

Research

Evaluating IOMMU-Based Shared Virtual Addressing for RISC-V Embedded Heterogeneous SoCs

Abstract This work quantitatively evaluates Input-Output Memory Management Unit (IOMMU)-based Shared Virtual Addressing (SVA) for RISC-V embedded heterogeneous SoCs, enabling zero-copy data offloading between host and accelerator. While IO

By Admin 24 Feb 2025 • 2 min read •

Research

What’s on tap from RISC-V in 2025? - Jon Peddie Research

Abstract The analysis from Jon Peddie Research forecasts the critical trends and commercial trajectory of the RISC-V architecture expected throughout 2025. It predicts a significant push beyond embedded systems, focusing on higher-

By Admin 24 Feb 2025 • 2 min read •

Research

What’s on tap from RISC-V in 2025? - Jon Peddie

Abstract The analysis by Jon Peddie forecasts the significant technological advancements and market shifts anticipated within the RISC-V ecosystem through 2025. The article highlights the architecture's accelerated push into mainstream

By Admin 24 Feb 2025 • 2 min read •

Research

Translating Common Security Assertions Across Processor Designs: A RISC-V Case Study

Abstract This work introduces a novel methodology for translating pre-defined security assertions across disparate processor architectures, addressing the high cost and complexity of manual verification, especially within the growing RISC-V ecosystem.

By Admin 14 Feb 2025 • 2 min read •

Research

A Novel Approach to Reducing Testing Costs and Minimizing Defect Escapes Using Dynamic Neighborhood Range and Shapley Values

Abstract This article presents a novel verification methodology aimed at substantially reducing hardware testing costs while simultaneously minimizing defect escapes. The approach integrates Dynamic Neighborhood Range (DNR) algorithms for efficient adaptive test generation

By Admin 12 Feb 2025 • 2 min read •

Research

ISRO and IIT Madras jointly develop indigenous semiconductor chip for space-based applications - The Indian Express

Abstract ISRO and IIT Madras have jointly announced the successful development of an indigenous semiconductor chip designed specifically for space-based applications. This strategic collaboration aims to significantly advance India's self-

By Admin 12 Feb 2025 • 2 min read •

Research

Optimizing Energy Efficiency in Subthreshold RISC-V Cores

Abstract This study analyzes the energy efficiency of six open-source RISC-V cores operating in the subthreshold regime, utilizing a custom library targeting 300 mV in a 130 nm process. The core

By Admin 10 Feb 2025 • 2 min read •

Research

Croc: An End-to-End Open-Source Extensible RISC-V MCU Platform to Democratize Silicon

Abstract Croc is an end-to-end, free and open-source RISC-V microcontroller platform designed to democratize silicon access and bridge the gap between education and semiconductor innovation. The platform features a

By Admin 7 Feb 2025 • 2 min read •

Research

Comprehensive Formal Verification of Observational Correctness for the CHERIoT-Ibex Processor

Abstract This paper reports the first comprehensive formal verification of observational correctness for the CHERIoT-Ibex processor, a RISC-V core implementing the security-focused CHERI architecture with complex, internally compressed capabilities. Utilizing

By Admin 7 Feb 2025 • 2 min read •