Research

Fused-Tiled Layers: Minimizing Data Movement on RISC-V SoCs with Software-Managed Caches

Abstract This work introduces Fused-Tiled Layers (FTL), a novel algorithm designed for the automatic fusion of tiled layers in Deep Neural Networks (DNNs) to minimize excessive data movement. FTL addresses the common issue

By Admin 21 Mar 2025 • 2 min read •

Research

MemPool Flavors: Between Versatility and Specialization in a RISC-V Manycore Cluster

Originally published on ArXiv - Hardware Architecture Computer Science > Hardware Architecture arXiv:2504.03675v1 (cs) [Submitted on 21 Mar 2025] Title:MemPool Flavors: Between Versatility and Specialization in a RISC-V Manycore Cluster

By Admin 21 Mar 2025 • 3 min read •

Research

NeCTAr: A Heterogeneous RISC-V SoC for Language Model Inference in Intel 16

Abstract NeCTAr (Near-Cache Transformer Accelerator) is a 16nm heterogeneous multicore RISC-V System-on-Chip (SoC) integrating near-core and near-memory accelerators optimized for efficient sparse and dense machine learning inference. The prototype chip, designed for language

By Admin 18 Mar 2025 • 2 min read •

Research

HERMES: High-Performance RISC-V Memory Hierarchy for ML Workloads

Abstract HERMES proposes a high-performance memory hierarchy specifically for RISC-V architectures executing demanding ML workloads like CNNs and Transformers. The core innovation involves integrating shared L3 caches with fine-grained coherence protocols and specialized

By Admin 17 Mar 2025 • 1 min read •

Research

Open-source chip design spurring on AI - China Daily

Abstract The article details how the emerging open-source chip design movement, centered likely around the RISC-V instruction set architecture, is becoming a primary catalyst for accelerating artificial intelligence development. This trend significantly lowers

By Admin 13 Mar 2025 • 2 min read •

Research

Maestro: A 302 GFLOPS/W and 19.8GFLOPS RISC-V Vector-Tensor Architecture for Wearable Ultrasound Edge Computing

Abstract Maestro is a RISC-V System-on-Chip featuring a unified Vector-Tensor Unit (VTU) and specialized FFT accelerators, designed for highly efficient, on-device signal processing in Wearable Ultrasound (WUS) edge computing. Fabricated in low-cost 65nm

By Admin 6 Mar 2025 • 2 min read •

Research

CRAFT: Characterizing and Root-Causing Fault Injection Threats at Pre-Silicon

Abstract CRAFT is a novel framework that utilizes pre-silicon analysis to efficiently characterize and root-cause fault injection vulnerabilities in processor designs, substantially reducing the search space for post-silicon validation. Applied to a RISC-V

By Admin 5 Mar 2025 • 2 min read •

Research

Honest to a Fault: Root-Causing Fault Attacks with Pre-Silicon RISC Pipeline Characterization

Abstract This paper presents a comprehensive methodology for conducting and root-causing controlled fault injection attacks at the pre-silicon level, tracing fault propagation from the physical layer to the system software. The study applies

By Admin 5 Mar 2025 • 2 min read •

Research

When Radiation Meets Linux: Analyzing Soft Errors in Linux on COTS SoCs under Proton Irradiation

Abstract This study analyzes the vulnerability of Linux running on Commercial Off-The-Shelf (COTS) System-on-Chips (SoCs) to radiation-induced soft errors using 20-50 MeV proton irradiation. Testing diverse architectures, including ARM Cortex-A53 (14 nm FinFET

By Admin 5 Mar 2025 • 2 min read •

News

Exclusive: China to publish policy to boost RISC-V chip use nationwide, sources say - Reuters

Abstract China is preparing to publish a significant national policy designed to aggressively boost the use of RISC-V chips across various sectors nationwide. This governmental initiative signals a strategic commitment to standardizing the

By Admin 4 Mar 2025 • 2 min read •

Research

RISC-V High Performance Multicore and GPU SoC Platform For Safety Critical System - Semiconductor Engineering

Abstract This article details a new System-on-Chip (SoC) platform built on the RISC-V Instruction Set Architecture, specifically designed for stringent safety-critical systems. The platform integrates high-performance multicore CPU clusters alongside an integrated GPU,

By Admin 3 Mar 2025 • 2 min read •

Research

DeepVerifier: Learning to Update Test Sequences for Coverage-Guided Verification

Abstract DeepVerifier introduces a novel machine learning framework designed to optimize hardware verification efficiency by intelligently updating existing test sequences for coverage closure. The system utilizes deep reinforcement learning (DRL) to guide the

By Admin 1 Mar 2025 • 2 min read •