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Research
Hardware/Software Co-Design of RISC-V Extensions for Accelerating Sparse DNNs on FPGAs
Abstract
This paper proposes novel RISC-V instruction set extensions designed through hardware/software co-design to efficiently accelerate sparse Deep Neural Networks (DNNs) on FPGAs. The design introduces custom functional units: one
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Sustaining Standards Leadership: The United States Cannot Disengage from RISC-V - CSIS | Center for Strategic and International Studies
Abstract
The Center for Strategic and International Studies (CSIS) asserts that the U.S. must remain deeply engaged in the open-source RISC-V instruction set architecture (ISA) standards development. Disengagement risks relinquishing
Research
A 10-cent RISC-V microcontroller from China? Why not? - EEJournal
Abstract
The EEJournal article highlights the emergence of an ultra-low-cost RISC-V microcontroller from a Chinese manufacturer, setting a revolutionary price point of approximately 10 cents USD. This development signifies a
Research
Zoozve: A Strip-Mining-Free RISC-V Vector Extension with Arbitrary Register Grouping Compilation Support (WIP)
Abstract
The Zoozve instruction extension addresses performance limitations in the standard RISC-V Vector Extension (RVV), specifically those caused by static register counts and required strip-mining for long vectors. Zoozve is a
Research
CVA6S+: A Superscalar RISC-V Core with High-Throughput Memory Architecture
Abstract
CVA6S+ is an enhanced, open-source superscalar RISC-V core featuring optimized microarchitectural components like improved branch prediction and register renaming. These enhancements lead to a 43.5% performance increase over the
Research
Alibaba’s AI cancer detection tool clears FDA hurdle for faster approval process - South China Morning Post
Abstract
Alibaba’s Artificial Intelligence (AI) tool designed for cancer detection has achieved a crucial milestone by clearing a significant hurdle set by the U.S. Food and Drug Administration (FDA). This regulatory
Research
DataMaestro: A Versatile and Efficient Data Streaming Engine Bringing Decoupled Memory Access To Dataflow Accelerators
Abstract
DataMaestro is a novel data streaming engine that applies a decoupled access/execute architecture to Deep Neural Network (DNN) dataflow accelerators to mitigate performance bottlenecks caused by data movement. It features programmable
Research
VEXP: A Low-Cost RISC-V ISA Extension for Accelerated Softmax Computation in Transformers
Abstract
The VEXP project introduces a low-cost RISC-V Instruction Set Architecture (ISA) extension specifically designed to accelerate the Softmax computation bottleneck found in modern Transformer models. This is achieved by integrating
Research
Unlimited Vector Processing for Wireless Baseband Based on RISC-V Extension
Abstract
This paper introduces the Unlimited Vector Processing (UVP) instruction set extension for RISC-V, specifically targeting performance improvements in wireless baseband processing (WBP). UVP overcomes conventional vector architecture constraints by implementing a
Research
AraOS: Analyzing the Impact of Virtual Memory Management on Vector Unit Performance
Abstract
This work introduces AraOS, an integrated environment enabling full operating system (Linux) support for the open-source Ara2 RISC-V vector processor by sharing the Memory Management Unit (MMU) of the CVA6
Research
Efficient Architecture for RISC-V Vector Memory Access
Abstract
Vector processors frequently suffer from inefficient memory accesses, particularly for strided and segment patterns, often relying on high-overhead crossbars or large transposition buffers. This paper presents EARTH, a novel RISC-V