Research

Introducing Instruction-Accurate Simulators for Performance Estimation of Autotuning Workloads

Abstract This paper introduces a novel interface enabling autotuning workloads, critical for optimizing Machine Learning, to execute efficiently on instruction-accurate simulators rather than scarce target hardware. By training machine learning predictors on simulation

By Admin 19 May 2025 • 2 min read •

Research

MXDOTP: A RISC-V ISA Extension for Enabling Microscaling (MX) Floating-Point Dot Products

Abstract MXDOTP is a novel RISC-V ISA extension designed to accelerate dot product computations using the energy-efficient and highly accurate 8-bit Microscaling Floating-Point (MXFP8) format. The extension integrates a specialized MXFP8 dot product-accumulate

By Admin 19 May 2025 • 2 min read •

Research

AES-RV: Hardware-Efficient RISC-V Accelerator with Low-Latency AES Instruction Extension for IoT Security

Abstract The AES-RV paper presents a hardware-efficient RISC-V accelerator featuring custom, low-latency AES instruction extensions optimized for real-time cryptographic processing in IoT systems. The architecture integrates high-bandwidth buffers, a specialized AES unit, and

By Admin 17 May 2025 • 1 min read •

News

Automotive Industry Charts New Course with RISC-V - EE Times

Abstract The automotive industry is strategically shifting towards the open-standard RISC-V instruction set architecture, marking a pivotal moment in vehicle semiconductor design. This adoption is driven by the industry's need for

By Admin 16 May 2025 • 2 min read •

Research

Scalable 28nm IC implementation of coupled oscillator network featuring tunable topology and complexity

Abstract This work introduces a scalable, 28nm integrated circuit implementation of a coupled oscillator network designed to efficiently simulate complex dynamical systems for applications like analog computing and transport network stability analysis. The

By Admin 15 May 2025 • 2 min read •

Research

Enabling Syscall Intercept for RISC-V

Abstract This paper details the efforts involved in porting a widely used syscall interception library to the RISC-V Instruction Set Architecture. The work is crucial for maturing the RISC-V software stack, enabling complex

By Admin 15 May 2025 • 1 min read •

Research

An Integrated UVM-TLM Co-Simulation Framework for RISC-V Functional Verification and Performance Evaluation

Abstract This paper introduces an integrated UVM-TLM co-simulation framework designed to efficiently verify complex RISC-V processors by simultaneously evaluating functional correctness and performance. The methodology employs a configurable Transaction-Level Model (vmodel) of a

By Admin 15 May 2025 • 1 min read •

Research

Basilisk: A 34 mm2 End-to-End Open-Source 64-bit Linux-Capable RISC-V SoC in 130nm BiCMOS

Abstract The Basilisk project introduces the largest end-to-end open-source system-on-chip (SoC) to date, successfully integrating a 64-bit Linux-capable RISC-V core on a 34 mm² die. Implemented in 130 nm BiCMOS technology, this effort

By Admin 15 May 2025 • 2 min read •

Research

Embedded GPU: An Open-Source And Configurable RISC-V GPU Platform for TinyAI Devices (EPFL) - Semiconductor Engineering

Abstract EPFL has introduced the Embedded GPU (eGPU), an open-source and highly configurable GPU platform based on the RISC-V instruction set architecture. This innovation is specifically designed to accelerate graphics and computation tasks

By Admin 14 May 2025 • 2 min read •

Research

Area Comparison of CHERIoT and PMP in Ibex

Abstract This paper analyzes the hardware area cost of implementing Physical Memory Protection (PMP) and the CHERIoT capability-based security extension within the Ibex RISC-V core. Synthesis results show that PMP (16 regions) adds

By Admin 13 May 2025 • 2 min read •

Research

AiTPO: KAN-UNet Heterogeneous Network for Timing Prediction and Optimization at Global Routing

Abstract AiTPO presents a novel framework utilizing a heterogeneous KAN-UNet network architecture designed for highly accurate timing prediction and optimization during the critical global routing phase of IC design. By integrating the localized

By Admin 13 May 2025 • 2 min read •

Research

e-GPU: An Open-Source and Configurable RISC-V Graphic Processing Unit for TinyAI Applications

Abstract This work introduces e-GPU, an open-source and highly configurable RISC-V Graphic Processing Unit designed to deliver parallel acceleration to ultra-low-power TinyAI devices. The platform utilizes a lightweight Tiny-OpenCL framework for programming and

By Admin 13 May 2025 • 2 min read •