Research

FREESS: An Educational Simulator of a RISC-V-Inspired Superscalar Processor Based on Tomasulo's Algorithm

Originally published on ArXiv - Hardware Architecture Computer Science > Hardware Architecture arXiv:2506.07665v1 (cs) [Submitted on 9 Jun 2025] Title:FREESS: An Educational Simulator of a RISC-V-Inspired Superscalar Processor Based on

By Admin 9 Jun 2025 • 4 min read •

Research

Chip Industry Technical Paper Roundup: June 9 - Semiconductor Engineering

Abstract The Chip Industry Technical Paper Roundup for June 9 compiles recent research breakthroughs across various facets of semiconductor technology. The featured papers generally focus on overcoming scaling limitations, implementing advanced 2.5D/

By Admin 9 Jun 2025 • 2 min read •

News

Momentum Builds on RISC-V European Adoption - EE Times

Abstract The article reports a significant acceleration in the adoption of the RISC-V instruction set architecture (ISA) across Europe. This growing momentum is driven by increasing industrial investment and academic collaboration seeking open

By Admin 9 Jun 2025 • 1 min read •

Research

ASPO: Constraint-Aware Bayesian Optimization for FPGA-based Soft Processors

Abstract ASPO (Constraint-Aware Bayesian Optimization) is a novel approach designed to efficiently tune parameters for complex FPGA-based soft processors, overcoming limitations of standard Bayesian Optimization concerning categorical constraints and lengthy optimization times. The

By Admin 7 Jun 2025 • 2 min read •

Research

Design and Implementation of a RISC-V SoC with Custom DSP Accelerators for Edge Computing

Abstract This paper analyzes the performance of a custom RISC-V SoC implementation, utilizing the RV32I base ISA with M and A extensions, specifically targeting edge computing applications. Through cycle-accurate simulation, the pipelined design

By Admin 7 Jun 2025 • 1 min read •

Research

Open-Source RISC-V Cores: Analysis Of Scalar and Superscalar Architectures And Out-Of-Order Machines - Semiconductor Engineering

Abstract The article analyzes the diverse architectural landscape of open-source RISC-V cores, contrasting simple scalar designs with complex superscalar and out-of-order machines. It examines the critical engineering trade-offs between design complexity, power consumption,

By Admin 5 Jun 2025 • 2 min read •

Research

Ramping Up Open-Source RISC-V Cores: Assessing the Energy Efficiency of Superscalar, Out-of-Order Execution

Abstract This work standardizes the proprietary XuanTie C910 Out-of-Order (OoO) RISC-V core for full compliance and introduces CVA6S+, an enhanced dual-issue version of the CVA6 core, achieving a 34.4% performance boost. A

By Admin 30 May 2025 • 2 min read •

Research

Enable Lightweight and Precision-Scalable Posit/IEEE-754 Arithmetic in RISC-V Cores for Transprecision Computing

Abstract This paper presents a novel, unified hardware solution for integrating lightweight and precision-scalable Posit arithmetic into RISC-V Floating Point Units (FPU), while maintaining compatibility with IEEE-754 standards. The implementation uses dedicated posit

By Admin 25 May 2025 • 2 min read •

Research

Modular SAIL: dream or reality?

Abstract This paper addresses the critical challenge of compositionality in the RISC-V development flow, which is necessary to fully leverage the modular nature of the ISA specification. The authors introduce "modular SAIL,

By Admin 22 May 2025 • 2 min read •

News

RISC-V Turns 15 With Fast Global Adoption - EE Times

Abstract RISC-V celebrates its 15th anniversary, signifying a major milestone for the open standard Instruction Set Architecture (ISA). The architecture is currently experiencing explosive, rapid global adoption, moving far beyond its academic roots

By Admin 22 May 2025 • 2 min read •

Research

RISC-Q: A Generator for Real-Time Quantum Control System-on-Chips Compatible with RISC-V

Abstract RISC-Q is introduced as an open-source, flexible generator for Quantum Control System-on-Chips (QCSoC) designed to meet the stringent, real-time demands of large-scale qubit systems. It addresses the fragmentation and scalability issues of

By Admin 20 May 2025 • 2 min read •

Research

Chip Industry Technical Paper Roundup: May 20 - Semiconductor Engineering

Abstract The "Chip Industry Technical Paper Roundup: May 20" likely summarizes significant recent research across the semiconductor ecosystem, addressing critical challenges in scaling, power efficiency, and advanced manufacturing. Key topics typically

By Admin 20 May 2025 • 2 min read •