News

MuseLab Launches the $3.50 nanoCH57x, Building on WCH Electronics' CH570D RISC-V Part - Hackster.io

Originally published on Google News - RISC-V MuseLab Launches the $3.50 nanoCH57x, Building on WCH Electronics' CH570D RISC-V Part  Hackster.io AI Analysis Key Highlights * Product Launch: MuseLab introduced the nanoCH57x

By Admin 18 Jun 2025 • 1 min read •

Research

Acore-CIM: build accurate and reliable mixed-signal CIM cores with RISC-V controlled self-calibration

Abstract Acore-CIM introduces a self-calibrated mixed-signal Compute-In-Memory (CIM) System-on-Chip (SoC) designed to overcome the integration and reliability challenges of analog AI accelerators. The architecture pairs dense SRAM weight storage with linear resistors for

By Admin 18 Jun 2025 • 2 min read •

News

$3.50 nanoCH57x CH570/CH572 RISC-V development board offers USB-C port, 2.4GHz radio/BLE, and GPIO pins - CNX Software

Abstract CNX Software reports on the launch of the nanoCH57x development board, featuring a CH570/CH572 RISC-V microcontroller at an aggressive price point of just $3.50. This ultra-affordable board is designed for

By Admin 18 Jun 2025 • 1 min read •

Research

Chip Industry Technical Paper Roundup: June 17 - Semiconductor Engineering

Abstract This analysis reviews the scope of the 'Chip Industry Technical Paper Roundup: June 17' by Semiconductor Engineering. Due to the absence of the actual article content, a detailed summary of

By Admin 17 Jun 2025 • 1 min read •

News

Indian RISC-V Startup Slashes Design Time to Minutes - EE Times

Abstract An Indian RISC-V startup has achieved a significant technological breakthrough by developing a system that drastically reduces processor design time. This innovation allows users to configure and generate customized RISC-V core IP

By Admin 17 Jun 2025 • 2 min read •

News

The Rise of RISC-V ... - eeNews Europe

Abstract The article details the substantial acceleration and maturation of the RISC-V open Instruction Set Architecture (ISA), positioning it as a significant challenger to proprietary alternatives like Arm. This rise is fueled by

By Admin 16 Jun 2025 • 2 min read •

Research

FeNN: A RISC-V vector processor for Spiking Neural Network acceleration

Abstract The FeNN processor is a novel RISC-V-based soft vector processor specifically tailored for simulating energy-efficient Spiking Neural Networks (SNNs) on FPGAs. Unlike mainstream accelerators, FeNN is optimized for the low arithmetic intensity

By Admin 13 Jun 2025 • 2 min read •

Research

FractalSync: Lightweight Scalable Global Synchronization of Massive Bulk Synchronous Parallel AI Accelerators

Abstract FractalSync is a novel hardware-accelerated synchronization mechanism designed to address the challenges of coordinating massive parallel processing elements in Bulk Synchronous Parallel (BSP) AI accelerators. Integrated into the RISC-V based MAGIA platform,

By Admin 13 Jun 2025 • 2 min read •

Research

Towards Zero-Stall Matrix Multiplication on Energy-Efficient RISC-V Clusters for Machine Learning Acceleration

Abstract This paper presents microarchitectural optimizations for energy-efficient RISC-V clusters aimed at achieving near zero-stall matrix multiplication for machine learning workloads. Key innovations include "zero-overhead loop nests" and a novel "

By Admin 12 Jun 2025 • 2 min read •

News

RISC-V’s Increasing Influence - Semiconductor Engineering

Abstract RISC-V is rapidly increasing its influence across the semiconductor industry, expanding adoption beyond academic and niche markets into high-volume segments like data centers, automotive, and consumer electronics. This growth is fundamentally driven

By Admin 12 Jun 2025 • 2 min read •

Research

Towards Base-Station-On-Chip: Wireless Communication Kernels On A RISC-V Vector Processor (TU Dresden, CeTI) - Semiconductor Engineering

Abstract Researchers from TU Dresden's Center for Tactile Internet (CeTI) are investigating the potential of the RISC-V Vector Processor to efficiently handle demanding wireless communication kernels. This research aims to prove

By Admin 10 Jun 2025 • 2 min read •

Research

FREESS: An Educational Simulator of a RISC-V-Inspired Superscalar Processor Based on Tomasulo's Algorithm

Abstract FREESS is a new free, interactive educational simulator designed to teach instruction-level parallelism in advanced computer architecture courses. It models a RISC-V-inspired superscalar processor utilizing an extended Tomasulo's algorithm for

By Admin 9 Jun 2025 • 1 min read •