Research

MARVEL: An End-to-End Framework for Generating Model-Class Aware Custom RISC-V Extensions for Lightweight AI

Abstract MARVEL is an automated, end-to-end framework designed to efficiently deploy deep neural networks (DNNs) on highly resource-constrained IoT devices operating in bare-metal environments. It achieves this by generating custom RISC-V Instruction Set

By Admin 3 Aug 2025 • 2 min read •

Research

A Dynamic Allocation Scheme for Adaptive Shared-Memory Mapping on Kilo-core RV Clusters for Attention-Based Model Deployment

Abstract This paper presents the Dynamic Allocation Scheme (DAS) to resolve severe shared L1 memory contention and underutilization issues in kilo-core RISC-V clusters designed for attention-based models. DAS is a runtime programmable address

By Admin 2 Aug 2025 • 2 min read •

Research

Smart Video Capsule Endoscopy: Raw Image-Based Localization for Enhanced GI Tract Investigation

Abstract This work introduces an ultra-low power AI solution for Smart Video Capsule Endoscopy, addressing severe battery life limitations in medical edge devices. The innovation involves performing accurate organ classification (93.06% accuracy)

By Admin 31 Jul 2025 • 2 min read •

Research

Discover the Top 10 Semiconductor Trends in 2026 - StartUs Insights

Originally published on Google News - RISC-V Research Discover the Top 10 Semiconductor Trends in 2026  StartUs Insights

By Admin 29 Jul 2025 •

Research

Chip Industry Technical Paper Roundup: July 29 - Semiconductor Engineering

Abstract The 'Chip Industry Technical Paper Roundup' from Semiconductor Engineering summarizes cutting-edge advancements across the semiconductor industry, covering fundamental research in manufacturing, materials science, and chip architecture. These roundups are vital

By Admin 29 Jul 2025 • 2 min read •

News

RISC-V Market Size, Share & Growth Report, 2025-2034 - Global Market Insights Inc.

Abstract This market analysis projects significant growth for the global RISC-V ecosystem, spanning the decade from 2025 to 2034. The report details forecasts concerning market size, share, and revenue growth across various sectors

By Admin 29 Jul 2025 • 2 min read •

News

RISC-V’s Ascent Could Reshape The Global Compute Landscape - Forbes

Abstract The article analyzes the rapid market penetration of the RISC-V Instruction Set Architecture (ISA), positioning it as a major force capable of disrupting the global compute landscape currently dominated by proprietary designs

By Admin 24 Jul 2025 • 2 min read •

News

NVIDIA Confirms CUDA Support Is Coming To RISC-V And It's A Huge Deal - HotHardware

Abstract NVIDIA has officially confirmed that its proprietary parallel computing platform, CUDA, will be ported to the open-source RISC-V instruction set architecture (ISA). This development is a pivotal moment, effectively bridging the gap

By Admin 23 Jul 2025 • 1 min read •

News

How Next-Gen Chips Are Unlocking RISC-V’s Customization Advantage - Design And Reuse

Abstract Next-generation chip architectures and advanced integration techniques are proving critical in fully unlocking the inherent customization and extensibility advantages of the RISC-V Instruction Set Architecture (ISA). This synergy allows designers to rapidly

By Admin 23 Jul 2025 • 2 min read •

News

NVIDIA Confirms CUDA Support Is Coming To RISC-V And It's A Huge Deal - HotHardware

Originally published on Google News - RISC-V NVIDIA Confirms CUDA Support Is Coming To RISC-V And It's A Huge Deal  HotHardware AI Analysis Key Highlights * Official Confirmation: NVIDIA has committed to

By Admin 23 Jul 2025 • 1 min read •

News

Inside Cyient Semiconductors Bet on RISC-V for Custom Silicon - EE Times

Abstract Cyient Semiconductors is making a significant strategic commitment by centering its custom silicon design services around the open-source RISC-V instruction set architecture. This focus aims to capitalize on the burgeoning market demand

By Admin 22 Jul 2025 • 2 min read •

Research

Tag-Based Memory Verification System for RISC-V (Inha Univ., Intel Labs et al.) - Semiconductor Engineering

Abstract Researchers from Inha University and Intel Labs have jointly developed a novel Tag-Based Memory Verification System optimized for the RISC-V architecture. This hardware-assisted security mechanism utilizes tags, or metadata, associated with memory

By Admin 22 Jul 2025 • 2 min read •