Research

Support Vector Machines Classification on Bendable RISC-V

Abstract This paper addresses the challenge of implementing power-hungry Machine Learning (ML) algorithms on ultra-low-cost, lightweight Flexible Electronics (FE). The authors propose an open-source framework and a custom, precision-scalable Support Vector Machine (SVM)

By Admin 27 Aug 2025 • 2 min read •

Research

Building an Open CGRA Ecosystem for Agile Innovation

Abstract This paper presents a comprehensive, open-source ecosystem centered on Coarse-Grained Reconfigurable Architectures (CGRAs) to enable agile hardware-software co-design for AI and edge computing workloads. Key contributions include HyCUBE, a novel CGRA with

By Admin 26 Aug 2025 • 2 min read •

News

Condor Computing’s Cuzco, a High-Perf RISC-V Design at Hot Chip 2025 - ServeTheHome

Abstract Condor Computing is set to unveil "Cuzco," a new high-performance processor design based on the open RISC-V instruction set architecture. This crucial development targets the demanding high-end computing sector, signaling

By Admin 25 Aug 2025 • 2 min read •

Research

X-HEEP: An Open-Source, Configurable and Extendible RISC-V Platform for TinyAI Applications

Abstract X-HEEP is an open-source, configurable RISC-V platform specifically designed for ultra-low-power edge applications (TinyAI). Its key innovation is the eXtendible Accelerator InterFace (XAIF), which enables seamless, highly customizable integration of diverse accelerators,

By Admin 23 Aug 2025 • 2 min read •

Research

Targeted Wearout Attacks in Microprocessor Cores

Originally published on ArXiv - Hardware Architecture Computer Science > Cryptography and Security arXiv:2508.16868v1 (cs) [Submitted on 23 Aug 2025] Title:Targeted Wearout Attacks in Microprocessor Cores Authors:Joshua Mashburn, Johann

By Admin 23 Aug 2025 • 3 min read •

Research

Bare-Metal RISC-V + NVDLA SoC for Efficient Deep Learning Inference

Abstract This paper introduces a novel System-on-Chip (SoC) architecture that tightly couples a 32-bit Codasip uRISC_V core with the open-source NVDLA for efficient deep learning inference on edge devices. The core innovation

By Admin 22 Aug 2025 • 2 min read •

Research

Neural Network Quantization for Microcontrollers: A Comprehensive Survey of Methods, Platforms, and Applications

Abstract This comprehensive survey addresses the challenges of deploying Quantized Neural Networks (QNNs) on resource-constrained microcontrollers (MCUs) within the TinyML paradigm. It systematically reviews hardware-oriented quantization methods, focusing on the critical trade-offs between

By Admin 20 Aug 2025 • 2 min read •

Research

VTR 9: Open-Source CAD for Fabric and Beyond FPGA Architecture Exploration

Abstract VTR 9 represents a significant advancement in the open-source Verilog-to-Routing CAD flow, focusing on enabling comprehensive exploration of next-generation reconfigurable architectures. This release introduces powerful modeling capabilities for complex heterogeneous fabrics, moving

By Admin 19 Aug 2025 • 2 min read •

Research

IzhiRISC-V -- a RISC-V-based Processor with Custom ISA Extension for Spiking Neuron Networks Processing with Izhikevich Neurons

Abstract This paper presents IzhiRISC-V, a specialized RISC-V-compliant processor engineered to overcome the inherent inefficiency of running Spiking Neural Networks (SNNs) on general-purpose hardware. The core innovation is a custom Instruction Set Architecture

By Admin 18 Aug 2025 • 1 min read •

News

Former Intel chief architect launches RISC-V GPU startup - DIGITIMES Asia

Originally published on Google News - RISC-V Former Intel chief architect launches RISC-V GPU startup  DIGITIMES Asia

By Admin 14 Aug 2025 •

News

Former Intel chief architect launches RISC-V GPU startup - digitimes

Abstract A former chief architect from Intel has launched a new startup focused exclusively on designing Graphics Processing Units (GPUs) based on the open-source RISC-V instruction set architecture. This high-profile venture validates the

By Admin 14 Aug 2025 • 1 min read •

News

RISC-V basics: The truth about custom extensions - EDN - Voice of the Engineer

Abstract This article clarifies how the open and modular RISC-V architecture fundamentally facilitates the creation of custom instruction set extensions (ASIs). It details the mechanisms designers use, primarily reserved opcode space, to implement

By Admin 12 Aug 2025 • 1 min read •