News

SiFive introduces 2nd Gen Intelligence RISC-V AI CPUs: X160, X180, X280 Gen 2, X390 Gen 2, and XM Gen 2 - CNX Software

Abstract SiFive has officially introduced its second generation of Intelligence RISC-V AI CPUs, significantly expanding its processor portfolio dedicated to machine learning and AI acceleration. This new lineup includes fresh cores like the

By Admin 8 Sep 2025 • 2 min read •

News

SiFive enhances RISC-V IP with new features and upgrades - EDN - Voice of the Engineer

Abstract SiFive announced significant enhancements and upgrades across its RISC-V Intellectual Property (IP) portfolio, focusing on delivering higher performance and improved power efficiency for demanding applications. These updates integrate the latest RISC-V specifications

By Admin 8 Sep 2025 • 2 min read •

News

SiFive Unleashes Second-Generation RISC-V IP - EE Times

Abstract SiFive has officially unveiled its second generation of commercial RISC-V processor IP, marking a significant increase in performance and features aimed at high-demand markets. This new IP targets sophisticated applications, including data

By Admin 8 Sep 2025 • 2 min read •

News

SiFive Expands Its RISC-V Intelligence Family To Address Exploding AI Workloads - Forbes

Abstract SiFive announced a significant expansion of its RISC-V Intelligence processor family, specifically designed to meet the intensive computational demands of rapidly exploding AI workloads. This strategic launch provides chip designers with highly

By Admin 8 Sep 2025 • 2 min read •

News

Chip designer SiFive aims to cram more RISC-V cores into AI chips - theregister.com

Abstract Chip designer SiFive is strategically focusing its intellectual property (IP) development on high-performance artificial intelligence (AI) accelerators by aiming to significantly increase the density of RISC-V cores. This initiative seeks to leverage

By Admin 8 Sep 2025 • 2 min read •

News

RISC-V Zalasr Support Now Under Review For The Linux Kernel - Phoronix

Abstract Phoronix reports that support for the RISC-V Zalasr extension is currently under review for potential inclusion in the mainline Linux Kernel. This proposed extension aims to standardize and improve atomic load and

By Admin 5 Sep 2025 • 2 min read •

Research

basic_RV32s: An Open-Source Microarchitectural Roadmap for RISC-V RV32I

Abstract This paper introduces BASICRV32s, an open-source framework detailing a practical microarchitectural roadmap for the RISC-V RV32I Instruction Set Architecture. The design follows an evolutionary pathway, progressing from a basic single-cycle core to

By Admin 4 Sep 2025 • 2 min read •

Research

HEEPidermis: a versatile SoC for BioZ recording

Abstract HEEPidermis is a versatile System-on-Chip (SoC) designed to overcome the limitations of bulky, fixed-purpose hardware currently used for biological impedance (BioZ) recording. This SoC integrates a complete measurement pipeline, including specialized analog-to-digital

By Admin 3 Sep 2025 • 2 min read •

Research

Applications of AI in Space Domain

Abstract This comprehensive review examines the critical role of Artificial Intelligence in advancing autonomous space missions, spanning real-time data processing, celestial navigation, and on-board decision-making. The study highlights the significant architectural challenges associated

By Admin 3 Sep 2025 • 2 min read •

Research

Enhancing Large Language Models for Hardware Verification: A Novel SystemVerilog Assertion Dataset

Originally published on ACM Digital Library ACM Transactions on Design Automation of Electronic Systems, Volume 0, Issue ja, -Not available-.

By Admin 30 Aug 2025 •

Research

Microarchitecture Design and Benchmarking of Custom SHA-3 Instruction for RISC-V

Abstract This study designs and benchmarks a custom SHA-3 permutation instruction directly integrated into the RISC-V CPU microarchitecture to address the limitations of standalone cryptographic accelerators. Using cycle-accurate GEM5 simulations and FPGA prototyping,

By Admin 28 Aug 2025 • 2 min read •

Research

BePilot: An AI Programming Assistant for Compiler Backend Development

Abstract BePilot is introduced as a specialized AI programming assistant designed to streamline the complex, architecture-specific development of compiler backends. The assistant targets the automation of tedious or error-prone tasks such as instruction

By Admin 28 Aug 2025 • 2 min read •