Research

Automatic Microarchitecture-Aware Custom Instruction Design for RISC-V Processors

Abstract Designing Application-Specific Instruction Set Processors (ASIPs) requires the manual identification of performance-enhancing custom instructions, a process addressed by this work's new automation tool. The paper introduces CIDRE (Custom Instruction Designer

By Admin 19 Sep 2025 • 2 min read •

Research

MaRVIn: A Cross-Layer Mixed-Precision RISC-V Framework for DNN Inference, from ISA Extension to Hardware Acceleration

Abstract MaRVIn is a cross-layer hardware-software co-design framework that introduces novel ISA extensions and micro-architectural enhancements to optimize mixed-precision Deep Neural Network (DNN) inference on RISC-V processors. It tackles the inefficiency of standard

By Admin 18 Sep 2025 • 2 min read •

Research

HW/SW Co-Design to Retarget the Compiler For RISC-V Custom Instructions (Tampere Univ.) - Semiconductor Engineering

Abstract The research by Tampere University introduces an HW/SW co-design methodology aimed at efficiently integrating custom instruction set extensions (ISEs) into RISC-V cores. This approach specifically focuses on solving the typically time-consuming

By Admin 16 Sep 2025 • 2 min read •

News

RISC-V: Shaping the Future of Mobility with Open Standards - EE Times

Abstract RISC-V is emerging as the essential open standard architecture driving the future of mobility, specifically targeting advanced automotive applications like ADAS and high-performance computing in vehicles. The modular and customizable nature of

By Admin 16 Sep 2025 • 2 min read •

News

Condor Technology To Fly “Cuzco” RISC-V CPU Into The Datacenter - The Next Platform

Abstract Condor Technology is making a significant push into the competitive datacenter market with the introduction of its high-performance RISC-V CPU, codenamed "Cuzco." This development signals the maturity of the RISC-V

By Admin 15 Sep 2025 • 2 min read •

Research

SuperUROP: An FPGA-Based Spatial Accelerator for Sparse Matrix Operations

Abstract Solving sparse linear systems is critical in numerical methods but suffers from poor data reuse and complex dependencies on current hardware. This paper presents SuperUROP, an FPGA implementation of the Azul spatial

By Admin 15 Sep 2025 • 2 min read •

Research

TurboFuzz: FPGA Accelerated Hardware Fuzzing for Processor Agile Verification

Abstract TurboFuzz is an end-to-end hardware-accelerated verification framework that leverages a single FPGA to integrate the entire Test Generation, Simulation, and Coverage Feedback loop for modern processors. This architecture eliminates high host-FPGA communication

By Admin 12 Sep 2025 • 2 min read •

Research

Decentor-V: Lightweight ML Training on Low-Power RISC-V Edge Devices

Abstract This paper introduces Decentor-V, a framework that enables lightweight Machine Learning training directly on low-power RISC-V edge devices, overcoming the architectural limitation imposed by the absence of dedicated Floating-Point Units (FPUs). By

By Admin 10 Sep 2025 • 2 min read •

Research

FASE: FPGA-Assisted Syscall Emulation for Rapid End-to-End Processor Performance Validation

Abstract FASE (FPGA-Assisted Syscall Emulation) is a novel framework enabling rapid, early-stage processor performance validation by running complex multi-thread benchmarks directly on FPGA-hosted designs, bypassing the need for full SoC integration or a

By Admin 10 Sep 2025 • 2 min read •

News

SiFive Launches New RISC-V AI IP with Scalar, Vector, and Matrix Compute - eeNews Europe

Abstract SiFive has launched a new specialized RISC-V Intellectual Property (IP) core explicitly designed to accelerate Artificial Intelligence (AI) workloads. This new IP solution integrates comprehensive processing capabilities, combining traditional scalar processing with

By Admin 10 Sep 2025 • 2 min read •

Research

Lifetime-Aware Design of Item-Level Intelligence

Abstract We present FlexiFlow, a lifetime-aware design framework utilizing natively flexible electronics and area-optimized RISC-V cores for Item-Level Intelligence (ILI) embedded in disposable products. The framework addresses the 1000X operational lifetime variability in

By Admin 9 Sep 2025 • 2 min read •

News

SiFive details second generation RISC-V cores for AI accelerators ... - eeNews Europe

Abstract SiFive has announced details regarding its second generation of RISC-V cores specifically optimized for deployment within high-performance AI accelerators. This new product generation signals SiFive's strategy to capture the lucrative

By Admin 9 Sep 2025 • 2 min read •