Abstract The MUSE Book RISC-V laptop, featuring the SpacemiT K1/M1 octa-core SoC, demonstrates the maturation of the RISC-V hardware ecosystem into a consumer form factor. The 2026 review specifically prioritizes evaluating software progress, centering on the performance and usability of Bianbu OS 2.3 (Ubuntu 24.04-based). This analysis
Abstract This work introduces a novel approach for synthesizing practical Abstract Transformers tailored for the MLIR compiler infrastructure. By automating the generation of these crucial components, the system significantly reduces the manual engineering effort required to implement sound static analyses like data flow and shape inference. This methodology enhances the
Abstract ChiSA introduces a novel static analysis framework specifically designed for lightweight verification of hardware designs written in the Chisel HDL. This approach allows developers to detect common design errors, structural inconsistencies, and unsafe operations early in the development lifecycle without requiring resource-intensive simulation or heavy formal verification. By integrating
Abstract ArchSem introduces a novel, reusable framework for defining the rigorous semantics of complex relaxed computer architectures. This approach allows developers and verification engineers to formally specify weak memory models (WMMs) in a modular way, addressing the ambiguity inherent in natural language specifications. By providing a sound, compositional foundation, ArchSem
Abstract This article introduces a novel methodology for the foundational verification of running-time bounds, specifically addressing the complexities of interactive programs. It establishes a formal framework capable of mathematically certifying Worst-Case Execution Time (WCET) guarantees directly from the program's low-level semantics. This innovation ensures rigorous, formally proven timing