News

Why RISC-V + Blockchain Is the Conversation I’ve Been Waiting to Have - EE Times

Abstract The EE Times article highlights the critical intersection of the open-source RISC-V architecture and blockchain technology. This convergence is positioned to dramatically enhance hardware security and supply chain transparency, solving pervasive trust

By Admin 14 Oct 2025 • 2 min read •

Research

Sequencing on Silicon: AI SoC Design for Mobile Genomics at the Edge

Abstract This paper presents a specialized CMOS System-on-Chip (SoC) designed to handle the extremely high data rates of mobile nanopore DNA sequencing, advancing genomic analysis at the edge. The proposed architecture employs a

By Admin 10 Oct 2025 • 2 min read •

Research

A High-Efficiency SoC for Next-Generation Mobile DNA Sequencing

Abstract This paper presents a high-efficiency System-on-Chip (SoC) designed to enable truly mobile, real-time DNA sequencing by overcoming the computational limits of current hand-sized machines that rely on external processing. The SoC is

By Admin 10 Oct 2025 • 2 min read •

News

RISC-V set to announce 25% market penetration — open-standard ISA is ahead of schedule, securing fast-growing silicon footprint - Tom's Hardware

Abstract The open-standard RISC-V Instruction Set Architecture (ISA) is reportedly set to announce a significant achievement: 25% market penetration globally. This milestone demonstrates that RISC-V's growth is accelerating faster than predicted,

By Admin 9 Oct 2025 • 1 min read •

News

What Meta’s Purchase of Rivos Says About RISC-V - HPCwire

Abstract Meta's strategic acquisition of Rivos, a startup specializing in high-performance RISC-V chip design, validates the open-source architecture's maturity for demanding data center and AI workloads. This move allows

By Admin 8 Oct 2025 • 2 min read •

Research

A Dense and Efficient Instruction Set Architecture Encoding

Abstract This paper introduces Scry, a novel and experimental Instruction Set Architecture (ISA) designed to maximize instruction density and encoding efficiency for modern processor implementations. Scry achieves instruction-feature parity with RISC-V's

By Admin 5 Oct 2025 • 2 min read •

News

Terasic Announces Starter Kit Featuring RISC-V Nios V Processor and Software Bundle - LinuxGizmos.com

Abstract Terasic has announced the release of a new starter kit centered around the RISC-V Nios V processor, significantly aiding developers in exploring this architecture. The kit is packaged with essential hardware components

By Admin 3 Oct 2025 • 2 min read •

News

Quintauris and Everspin Technologies Partner to Advance Dependable RISC-V Solutions for Automotive - Business Wire

Abstract Quintauris and Everspin Technologies have partnered to develop dependable RISC-V solutions tailored for the demanding automotive sector. This strategic alliance aims to combine high-performance RISC-V processing with robust, non-volatile memory technologies to

By Admin 1 Oct 2025 • 2 min read •

News

Meta acquires RISC-V chip startup Rivos – report - Data Center Dynamics

Abstract Meta, the parent company of Facebook, is reportedly acquiring RISC-V chip startup Rivos, signaling a significant investment in custom silicon development. Rivos specializes in designing high-performance RISC-V processors intended for demanding data

By Admin 1 Oct 2025 • 2 min read •

News

Linus Torvalds Lashes Out At RISC-V Big Endian Plans - Phoronix

Abstract Linus Torvalds has vehemently criticized recent proposals to formally integrate Big Endian support within the RISC-V architecture specifications and the Linux kernel. Torvalds argues that adopting Big Endian introduces needless complexity, technical

By Admin 1 Oct 2025 • 2 min read •

Research

A Compact, Low Power Transprecision ALU for Smart Edge Devices

Abstract This work introduces TALU, a novel ASIC design for a Transprecision Arithmetic and Logic Unit tailored for energy-efficient machine learning on smart edge devices. TALU supports Posit, Floating Point, and Integer formats

By Admin 30 Sep 2025 • 2 min read •

Research

Runtime Energy Monitoring for RISC-V Soft-Cores

Abstract This paper introduces a holistic hardware-based approach for runtime energy monitoring specifically targeting RISC-V soft-cores implemented on FPGAs. The proposed system utilizes a dedicated measurement board coupled with an FPGA-based System-on-Module (SoM)

By Admin 30 Sep 2025 • 2 min read •