Research

SmaRTLy: RTL Optimization with Logic Inferencing and Structural Rebuilding

Abstract SmaRTLy is a novel RTL optimization technique specifically designed to enhance multiplexer tree synthesis by utilizing advanced logic inferencing and structural rebuilding methods. This approach overcomes the limitations of traditional synthesis tools

By Admin 20 Oct 2025 • 2 min read •

News

RISC-V deserves the same scrutiny China gives Nvidia - Washington Times

Abstract The article argues that the open-source nature of the RISC-V instruction set architecture (ISA) presents a significant national security risk, as it allows adversaries, primarily China, to circumvent US technology export controls.

By Admin 20 Oct 2025 • 2 min read •

Research

Architect in the Loop Agentic Hardware Design and Verification

Abstract This paper proposes an "Architect in the Loop" agentic framework that automates the systematic and hierarchical design and verification of complex digital hardware, particularly processors. The methodology utilizes a combination

By Admin 19 Oct 2025 • 2 min read •

Research

Chip Industry Week in Review - Semiconductor Engineering

Originally published on Google News - RISC-V Research Chip Industry Week in Review  Semiconductor Engineering

By Admin 17 Oct 2025 •

News

Upbeat Technology’s RISC-V MCU Takes Flight With Near-Threshold Computing - All About Circuits

Abstract Upbeat Technology has unveiled a new RISC-V Microcontroller Unit (MCU) that integrates sophisticated Near-Threshold Computing (NTC) technology. This innovation allows the chip to operate at minimal voltage levels, achieving dramatically improved energy

By Admin 17 Oct 2025 • 1 min read •

Research

SIMD-CP: SIMD with Redundant Bits Compression and Mixed-Precision Packing for Quantized DNNs

Abstract SIMD-CP is a novel architectural approach designed to significantly accelerate quantized Deep Neural Networks (DNNs) by enhancing Single Instruction, Multiple Data (SIMD) processing. It integrates redundant bits compression to reduce data transfer

By Admin 15 Oct 2025 • 2 min read •

News

Upbeat Technology and SiFive Introduce Next-Gen Ultra-Low Power RISC-V MCU with AI Acceleration - PR Newswire

Abstract Upbeat Technology and SiFive have jointly announced a next-generation Ultra-Low Power RISC-V Microcontroller Unit (MCU) designed specifically for advanced edge computing. The key innovation is the integration of dedicated AI acceleration capabilities

By Admin 15 Oct 2025 • 2 min read •

News

RISC-V International to announce 25% market penetration - New Electronics

Abstract RISC-V International is poised to announce a significant achievement: 25% market penetration for its open standard Instruction Set Architecture (ISA). This milestone signals the rapid transition of RISC-V from an academic curiosity

By Admin 15 Oct 2025 • 1 min read •

Research

ShuffleV: A Microarchitectural Defense Strategy against Electromagnetic Side-Channel Attacks in Microprocessors

Abstract ShuffleV is a novel microarchitectural defense strategy developed to counter Electromagnetic Side-Channel Attacks (EM SCAs) by adopting a Moving Target Defense (MTD) philosophy. It integrates hardware units into the open-source RISC-V core

By Admin 15 Oct 2025 • 2 min read •

Research

Near-Optimal Cache Sharing through Co-Located Parallel Scheduling of Threads

Abstract This work introduces a novel mechanism, Co-Located Parallel Scheduling, aimed at achieving near-optimal efficiency in shared cache utilization among competing threads. The innovation focuses on intelligently grouping and scheduling threads whose memory

By Admin 14 Oct 2025 • 2 min read •

Research

A Direct Memory Access Controller (DMAC) for Irregular Data Transfers on RISC-V Linux Systems

Abstract This paper introduces a novel Direct Memory Access Controller (DMAC) specifically optimized to efficiently handle arbitrary transfers of small unit sizes, addressing the inefficiency of classical descriptor-based DMACs in heterogeneous computing environments.

By Admin 14 Oct 2025 • 2 min read •

News

Forlinx OK153-S SBC Combines Cortex-A7 and RISC-V Cores for Real-Time I/O Interfaces - LinuxGizmos.com

Abstract The Forlinx OK153-S Single Board Computer (SBC) introduces a notable heterogeneous architecture combining an ARM Cortex-A7 core with a specialized RISC-V core. This design leverages the strengths of both platforms, using the

By Admin 14 Oct 2025 • 1 min read •