News

Developing RISC-V Compute Subsystems - Semiconductor Engineering

Abstract The article addresses the increasing complexity inherent in moving beyond standalone RISC-V core designs to developing fully integrated, high-performance compute subsystems crucial for modern SoCs. It highlights the architectural and methodological challenges

By Admin 29 Oct 2025 • 2 min read •

News

Bolt Graphics unveils Zeus GPU built on RISC-V and path tracing tech - theregister.com

Abstract Bolt Graphics has announced the Zeus GPU, a new graphics processing unit built entirely upon the open-source RISC-V instruction set architecture. The Zeus GPU distinguishes itself by incorporating advanced path tracing technology,

By Admin 29 Oct 2025 • 2 min read •

Research

Brevis Research Paper: ZKVM and Data Co-Processor - The Infinite Trustworthy Computing Layer - Bitget

Abstract Brevis's research outlines a novel architecture integrating a Zero-Knowledge Virtual Machine (ZKVM) with a dedicated Data Co-Processor to establish an "Infinite Trustworthy Computing Layer." This system is designed

By Admin 27 Oct 2025 • 2 min read •

Research

Proving and Rewarding Client Diversity to Strengthen Resilience of Blockchain Networks

Abstract This paper addresses the critical systemic risk in blockchain networks arising from the dominance of single client implementations by proposing mechanisms to prove and reward client diversity. The research details novel methods

By Admin 27 Oct 2025 • 2 min read •

News

RISC-V Exceeding Expectations in AI, China Deployment - EE Times

Abstract The RISC-V architecture is demonstrating growth rates that are significantly surpassing industry expectations, particularly within the critical domains of Artificial Intelligence and high-volume deployment across China. This acceleration is driven by the

By Admin 24 Oct 2025 • 2 min read •

News

Inside the RISC-V Hardware Wars: A Streetfighter’s Unfiltered Take - EEJournal

Abstract The article provides an unfiltered, 'streetfighter’s' perspective on the intense and rapidly escalating hardware wars surrounding the commercial adoption of the RISC-V instruction set architecture. It emphasizes the fierce

By Admin 23 Oct 2025 • 2 min read •

News

NextSilicon claims Maverick-2 accelerator outperforms Nvidia GPUs, plans new RISC-V test chip - Data Center Dynamics

Abstract NextSilicon has announced significant performance claims for its Maverick-2 accelerator, asserting it outperforms leading Nvidia GPUs in data center workloads. Furthermore, the company revealed strategic plans to develop a new RISC-V test

By Admin 22 Oct 2025 • 1 min read •

News

World’s Cheapest ARM Debugger Is Actually RISC-V - Hackaday

Abstract An analysis of the world's cheapest ARM debugger reveals that its core functionality is unexpectedly driven by a low-cost RISC-V microcontroller rather than traditional proprietary hardware. This innovation demonstrates the

By Admin 22 Oct 2025 • 1 min read •

Research

DRsam: Detection of Fault-Based Microarchitectural Side-Channel Attacks in RISC-V Using Statistical Preprocessing and Association Rule Mining

Abstract DRsam is a novel detection method addressing the vulnerability of RISC-V processors to fault-based microarchitectural side-channel attacks, a security area often neglected compared to x86 and ARM. This approach combines statistical preprocessing

By Admin 21 Oct 2025 • 1 min read •

News

Jon Peddie Research publishes Q3’25 RISC-V Market Update - Jon Peddie Research

Abstract Jon Peddie Research (JPR) has published its Q3 2025 Market Update dedicated to the rapidly evolving RISC-V ecosystem. This report provides crucial financial and market adoption data, tracking the commercial viability and

By Admin 21 Oct 2025 • 2 min read •

News

Jon Peddie Research publishes Q3’25 RISC-V Market Update - Jon Peddie

Originally published on Google News - RISC-V Jon Peddie Research publishes Q3’25 RISC-V Market Update  Jon Peddie

By Admin 21 Oct 2025 •

News

Upbeat and SiFive to Demonstrate Dual-Core RISC-V Microcontrollers with AI Acceleration at RISC-V Summit - Embedded Computing Design

Abstract Upbeat and SiFive plan to showcase dual-core RISC-V microcontrollers featuring integrated AI acceleration at the upcoming RISC-V Summit. This development highlights the maturation of RISC-V technology for complex edge computing applications requiring

By Admin 20 Oct 2025 • 1 min read •