Research

SynapticCore-X: A Modular Neural Processing Architecture for Low-Cost FPGA Acceleration

Abstract SynapticCore-X is a modular and open-source neural processing architecture optimized for resource-efficient deployment on low-cost FPGA platforms like the Zynq-7020. The design tightly couples a lightweight RV32IMC RISC-V control core with a

By Admin 16 Nov 2025 • 2 min read •

News

China's chip leaders bank on AI, EVs, RISC-V as industry's future growth engines - Yahoo Finance

Abstract China's leading semiconductor companies are strategically positioning artificial intelligence (AI), electric vehicles (EVs), and the open-source RISC-V architecture as the core pillars of the industry's future growth. This

By Admin 16 Nov 2025 • 2 min read •

News

China’s chip leaders bank on AI, EVs, RISC-V as industry’s future growth engines - South China Morning Post

Originally published on Google News - RISC-V China’s chip leaders bank on AI, EVs, RISC-V as industry’s future growth engines  South China Morning Post

By Admin 16 Nov 2025 •

News

China's chip leaders bank on AI, EVs, RISC-V as industry's future growth engines - Yahoo Finance

Originally published on Google News - RISC-V China's chip leaders bank on AI, EVs, RISC-V as industry's future growth engines  Yahoo Finance AI Analysis Key Highlights * Strategic Pivot: Chinese

By Admin 16 Nov 2025 • 2 min read •

News

China’s chip leaders bank on AI, RISC-V as industry’s growth engines - South China Morning Post

Abstract China's leading semiconductor manufacturers are strategically banking on Artificial Intelligence (AI) and the open-source RISC-V instruction set architecture as the primary engines for future industry growth. This strategic pivot aims

By Admin 16 Nov 2025 • 2 min read •

News

Mainline Linux Patches For The VisionFive 2 Lite: RISC-V For As Little As $19.9 USD - Phoronix

Abstract Mainline Linux kernel patches are being introduced for the VisionFive 2 Lite, a highly affordable RISC-V single-board computer (SBC) priced as low as $19.9 USD. This effort ensures robust, upstream support

By Admin 14 Nov 2025 • 1 min read •

Research

TeraPool: A Physical Design Aware, 1024 RISC-V Cores Shared-L1-Memory Scaled-Up Cluster Design With High Bandwidth Main Memory Link

Abstract The TeraPool project introduces a highly scaled-up cluster architecture integrating 1024 RISC-V cores optimized for parallelism. Its key innovation is a physically design-aware implementation featuring a shared-L1-memory structure, which enables ultra-low-latency data

By Admin 14 Nov 2025 • 2 min read •

Research

Sayram: A Hardware-software Co-design to Accelerate Wireless Baseband Processing

Abstract Sayram is a novel hardware-software co-design specifically developed to accelerate the computationally intensive tasks within wireless baseband processing, crucial for high-speed 5G communications. By integrating highly specialized hardware accelerators with optimized software

By Admin 13 Nov 2025 • 2 min read •

News

Openchip and NEC Moving Ahead with RISC-V VPUs for Aurora - HPCwire

Abstract Openchip and NEC are significantly advancing their collaborative efforts to integrate RISC-V Vector Processing Units (VPUs) within the high-performance computing (HPC) environment often associated with the 'Aurora' project. This partnership

By Admin 13 Nov 2025 • 1 min read •

Research

Optimized Hyperdimensional Edge AI Evaluation for Efficiency and Reliability under Real Radiation

Abstract This paper presents an optimized Hyperdimensional Computing (HDC) framework specifically designed for efficiency-critical Edge AI applications. The methodology focuses on achieving high computational efficiency while simultaneously maximizing reliability and fault tolerance in

By Admin 11 Nov 2025 • 2 min read •

Research

Decoupled Control Flow and Data Access in RISC-V GPGPUs

Abstract This paper addresses the performance limitations of Vortex, an open-source RISC-V GPGPU, by tackling high micro-code overheads associated with control flow (CF) management and memory access. The core innovation introduces decoupled CF

By Admin 10 Nov 2025 • 2 min read •

Research

FPGA-Accelerated RISC-V ISA Extensions for Efficient Neural Network Inference on Edge Devices

Abstract This paper presents novel FPGA-accelerated RISC-V instruction set architecture (ISA) extensions designed for efficient neural network inference on resource-constrained edge devices. The customized RISC-V core, featuring four domain-specific ISA extensions and integrated

By Admin 10 Nov 2025 • 2 min read •