Research

Vorion: A RISC-V GPU with Hardware-Accelerated 3D Gaussian Rendering and Training

Abstract Vorion is a novel RISC-V GPGPU prototype designed to provide dedicated hardware acceleration for the computationally intensive 3D Gaussian Splatting (3DGS) technique. It features a scalable architecture utilizing z-tiling and a Gaussian/

By Admin 20 Nov 2025 • 2 min read •

News

Wear This RISC V, RPN Calculator Watch For Maximum Nerd Cred - Hackaday

Abstract A new wearable project featuring an RPN calculator watch utilizes the open-source RISC-V architecture, specifically targeting technical enthusiasts. This device blends classic Reverse Polish Notation calculation methods with a modern, customized hardware

By Admin 20 Nov 2025 • 1 min read •

News

Fragmentation to Standardization: Evaluating RISC-V’s Path Across Data Centers, Automotive, and Security - embedded.com

Abstract The RISC-V architecture is undergoing a critical transition, moving from fragmented, custom implementations towards industry-wide standardization and compliance. This strategic shift is vital for securing necessary trust and adoption within high-stakes sectors

By Admin 20 Nov 2025 • 2 min read •

News

Canonical Gets Flutter Up And Running On RISC-V For Ubuntu - Phoronix

Abstract Canonical has successfully enabled the deployment of Google's Flutter UI toolkit on the RISC-V architecture running Ubuntu. This significant development enhances the application development landscape, offering developers a popular, cross-platform

By Admin 20 Nov 2025 • 1 min read •

News

Breker Verification Systems and Frontgrade Gaisler Collaborate on High-Reliability RISC-V Fault Tolerant Processor Core - Business Wire

Abstract Breker Verification Systems and Frontgrade Gaisler have partnered to develop a high-reliability, fault-tolerant RISC-V processor core. This collaboration leverages Breker's advanced verification automation tools to rigorously test the core'

By Admin 20 Nov 2025 • 1 min read •

Research

Toward Open-Source Chiplets for HPC and AI: Occamy and Beyond

Abstract This paper presents a roadmap for open-source RISC-V chiplet systems designed for high-performance computing (HPC) and artificial intelligence (AI), aiming to match the performance of proprietary architectures. The initiative introduces Occamy, the

By Admin 19 Nov 2025 • 2 min read •

Research

A Configurable Mixed-Precision Fused Dot Product Unit for GPGPU Tensor Computation

Abstract This paper introduces a scalable mixed-precision fused dot product unit designed to overcome the suboptimal throughput of discrete arithmetic units in GPGPUs for Deep Learning workloads. Integrated into the open-source RISC-V Vortex

By Admin 19 Nov 2025 • 2 min read •

News

RISC-V And Its Modularity Shine Across Applications - embedded.com

Abstract The article emphasizes that RISC-V’s success is intrinsically linked to its open standard and profound architectural modularity, enabling widespread adoption across diverse application spaces. This inherent flexibility permits designers to tailor

By Admin 19 Nov 2025 • 2 min read •

Research

CoroAMU: Unleashing Memory-Driven Coroutines through Latency-Aware Decoupled Operations

Abstract CoroAMU is a hardware-software co-designed system addressing severe memory latency issues in data-intensive applications running on disaggregated memory systems. The system features a compiler that optimizes coroutine management by minimizing context and

By Admin 19 Nov 2025 • 2 min read •

RISC-V

7 Things I Learned at RISC-V Summit North America 2025

Originally published on RISC-V International News * Tom GallVice President of Technology, RISC-V InternationalIndustry veteran Tom shapes the overall technical strategy for the RISC-V Instruction Set Architecture (ISA). An alum of IBM and Linaro,

By Admin 17 Nov 2025 • 5 min read •

News

Sailing Through the RISC-V Movement Across Continents - embedded.com

Abstract The article tracks the accelerated global momentum of the open-source RISC-V Instruction Set Architecture (ISA), highlighting its widespread adoption across various continents and industries. It emphasizes how this movement is transitioning from

By Admin 17 Nov 2025 • 1 min read •

News

d-Matrix and Andes Collaborate on RISC-V Accelerator for AI Inference - insidehpc.com

Abstract d-Matrix and Andes Technology have announced a strategic collaboration to develop a high-efficiency AI inference accelerator leveraging the open-standard RISC-V instruction set architecture. This partnership combines d-Matrix's specialized AI hardware

By Admin 17 Nov 2025 • 2 min read •