Research

RISC-V Based TinyML Accelerator for Depthwise Separable Convolutions in Edge AI

Abstract This paper introduces a novel RISC-V Custom Function Unit (CFU) accelerator designed for TinyML applications, targeting the high memory wall cost associated with Depthwise Separable Convolutions (DSCs). The architecture utilizes a fused

By Admin 26 Nov 2025 • 2 min read •

Research

Chip Industry Technical Paper Roundup: Nov. 26 - Semiconductor Engineering

Abstract This article compiles and summarizes recent technical papers detailing critical advancements across the semiconductor industry, focusing on cutting-edge R&D efforts. Key areas explored typically include solutions for managing power and

By Admin 26 Nov 2025 • 2 min read •

RISC-V

Enabling High Performance RISC-V Software for AI in the Real World

Abstract Embecosm demonstrated the successful acceleration of PyTorch AI workloads on RISC-V cores using the oneAPI Construction Kit. This effort, presented at RISC-V Europe 2025, showcased the portability of the unified oneAPI ecosystem,

By Admin 25 Nov 2025 • 2 min read •

News

Roadmap for Open-Source Chiplet-Based RISC-V Systems For HPC and AI (ETH Zurich, Univ. of Bologna) - Semiconductor Engineering

Abstract Researchers from ETH Zurich and the University of Bologna have proposed a definitive roadmap for creating next-generation HPC and AI systems based entirely on open-source RISC-V processors and modular chiplet architectures. This

By Admin 25 Nov 2025 • 2 min read •

Research

The Innovation Engine: Government-Funded Academic Research

Abstract This paper analyzes the crucial role of strategic government funding in incubating foundational technologies, specifically using the open-source development of the RISC-V Instruction Set Architecture (ISA) as a prime example. The research

By Admin 25 Nov 2025 • 2 min read •

Research

It’s the Specification, Stupid!

Abstract This article posits that the primary competitive advantage of the RISC-V architecture is its open, modular, and precise Instruction Set Architecture (ISA) specification, rather than any specific vendor implementation. The authors argue

By Admin 25 Nov 2025 • 2 min read •

Research

From University Research to Global Impact

Abstract The article traces the explosive growth and impact of the RISC-V Instruction Set Architecture (ISA), detailing its successful transition from academic research at UC Berkeley to a global, open-source hardware standard. It

By Admin 25 Nov 2025 • 2 min read •

Research

Taurus: Towards A High-Performance and Generic Congestion Control Framework for Datacenter Networks

Abstract Taurus introduces a novel and generic congestion control framework optimized for the unique demands of high-performance datacenter networks (DCNs). This framework is designed to overcome the inherent trade-off between maximizing network utilization

By Admin 25 Nov 2025 • 2 min read •

News

Offchain Labs challenges Vitalik's RISC-V proposal, says WASM better for Ethereum L1 - The Block

Abstract Offchain Labs, known for developing Arbitrum, has openly challenged Vitalik Buterin's proposal to adopt RISC-V as the future execution environment for the Ethereum Layer 1 (L1) blockchain. The company argues

By Admin 23 Nov 2025 • 1 min read •

News

Offchain Labs challenges Vitalik's RISC-V proposal, says WASM better for Ethereum L1 - The Block

Originally published on Google News - RISC-V Offchain Labs challenges Vitalik's RISC-V proposal, says WASM better for Ethereum L1  The Block AI Analysis Key Highlights * Offchain Labs publicly contested Vitalik Buterin&

By Admin 23 Nov 2025 • 1 min read •

News

RISC-V Testing Lapse Resulted In Wrong MIPS RISC-V Vendor ID Landing In Linux 6.18 - Phoronix

Abstract A significant testing lapse within the RISC-V architecture community resulted in an incorrect MIPS vendor ID being merged into the stable Linux 6.18 kernel release. This error could cause systems to

By Admin 22 Nov 2025 • 1 min read •

Research

Multi-Core Architecture Optimized For Time-Predictable Neural Network Inference (FZI, KIT) - Semiconductor Engineering

Abstract The research by FZI and KIT introduces a novel multi-core architecture specifically optimized to achieve time-predictable performance for Neural Network (NN) inference tasks. This design prioritizes deterministic latency guarantees over maximizing average

By Admin 21 Nov 2025 • 2 min read •