Research
Quark: An Integer RISC-V Vector Processor for Sub-Byte Quantized DNN Inference
Abstract
Quark is an integer RISC-V vector processor specifically tailored for highly efficient sub-byte quantized Deep Neural Network (DNN) inference. Built upon the open-source Ara processor, Quark achieves significant area and power savings
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Research
Is RISC-V Ready For Supercomputing? - Semiconductor Engineering
Abstract
The article evaluates the readiness of the open-source RISC-V architecture to meet the rigorous demands of High-Performance Computing (HPC) and supercomputing environments. While RISC-V offers key advantages like customization and potential power
Research
Adding Explicit Load-Acquire and Store-Release Instructions to the RISC-V ISA
Abstract
This paper proposes the addition of explicit load-acquire and store-release instructions to the RISC-V ISA, a crucial step for managing synchronization in architectures utilizing weak memory models. The authors demonstrate support by
Research
CVA6 RISC-V Virtualization: Architecture, Microarchitecture, and Design Space Exploration
Abstract
This article describes the implementation and optimization of hardware virtualization support for the open-source RISC-V CVA6 core, encompassing architecture and microarchitecture enhancements. The authors introduce specific structures like the G-Stage TLB (GTLB)
Research
RedMule: A Mixed-Precision Matrix-Matrix Operation Engine for Flexible and Energy-Efficient On-Chip Linear Algebra and TinyML Training Acceleration
Abstract
RedMulE is a specialized, mixed-precision matrix multiplication engine designed to enable energy-efficient TinyML training, which traditionally requires costly floating-point operations. Integrated into a RISC-V PULP cluster, the engine supports FP16 and hybrid
Research
TinyVers: A Tiny Versatile System-on-chip with State-Retentive eMRAM for ML Inference at the Extreme Edge
Abstract
TinyVers is an ultra-low power, versatile System-on-Chip designed for Machine Learning inference at the Extreme Edge, integrating a RISC-V host processor and a dataflow reconfigurable ML accelerator. The SoC leverages state-retentive embedded