Research
Simulation Environment with Customized RISC-V Instructions for Logic-in-Memory Architectures
Abstract
Addressing the challenges of the memory wall, this work proposes using customized RISC-V instructions to support Logic-in-Memory (LiM) operations within computing architectures. The key innovation is a modular, cycle-accurate simulation environment developed
Research
Hybrid Modular Redundancy: Exploring Modular Redundancy Approaches in RISC-V Multi-Core Computing Clusters for Reliable Processing in Space
Abstract
This paper presents Hybrid Modular Redundancy (HMR), a novel fault-tolerance scheme designed for RISC-V multi-core computing clusters intended for space applications. HMR enables flexible, on-demand dual-core or triple-core lockstep grouping with runtime
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Research
SwRI Is Researching ARM, RISC-V Processors For Use As Faster Spaceflight Computers - SpaceRef
Abstract
Southwest Research Institute (SwRI) is actively researching and evaluating modern processor architectures, specifically ARM and RISC-V, for future use in spaceflight computing systems. This effort aims to overcome the severe performance limitations
Research
ProSpeCT: Provably Secure Speculation for the Constant-Time Policy (Extended version)
Abstract
ProSpeCT is a generic formal processor model designed to provide provably secure speculative execution specifically for programs adhering to the constant-time policy. It guarantees security by tracking secret data within the pipeline
Research
ColibriES: A Milliwatts RISC-V Based Embedded System Leveraging Neuromorphic and Neural Networks Hardware Accelerators for Low-Latency Closed-loop Control Applications
Abstract
ColibriES is a novel milliwatt RISC-V based embedded system featuring the first-ever dedicated event-sensor interfaces and full neuromorphic processing pipelines. Built upon the Kraken System-on-Chip (SoC), it integrates a heterogeneous PULP processor
Research
RISE: RISC-V SoC for En/decryption Acceleration on the Edge for Homomorphic Encryption
Abstract
RISE is a novel RISC-V System-on-Chip (SoC) designed to accelerate critical message-to-ciphertext conversion operations for Homomorphic Encryption (HE) on resource-constrained edge devices. The architecture overcomes bottlenecks in error sampling and Number Theoretic