Research

Understanding Lasso and Jolt, from theory to code - a16z crypto

Abstract The article analyzes Lasso and Jolt, two recent cryptographic innovations designed to dramatically improve the efficiency of Zero-Knowledge (ZK) proving systems. Lasso introduces a highly optimized lookup argument that minimizes prover overhead

By Admin 10 Aug 2023 • 2 min read •

Research

Approaching the ‘lookup singularity’: Introducing Lasso and Jolt - a16z crypto

Abstract a16z crypto introduces Lasso and Jolt, a powerful combination of novel zero-knowledge proof (ZKP) systems designed to drastically improve computational efficiency. Lasso is a breakthrough approach to lookup arguments, significantly reducing the

By Admin 10 Aug 2023 • 2 min read •

Research

PPU: Design and Implementation of a Pipelined Full Posit Processing Unit (Full Report)

By Admin 7 Aug 2023 • 3 min read •

Research

PPU: Design and Implementation of a Pipelined Full Posit Processing Unit

Abstract This paper presents the design and integration of a Pipelined Full Posit Processing Unit (FPPU) into the low-power Ibex RISC-V core, leveraging the modular RISC-V ISA to enable customized posit arithmetic instructions.

By Admin 7 Aug 2023 • 2 min read •

Research

SoftFlow: Automated HW-SW Confidentiality Verification for Embedded Processors (Full Report)

By Admin 4 Aug 2023 • 3 min read •

Research

SoftFlow: Automated HW-SW Confidentiality Verification for Embedded Processors

Abstract SoftFlow is a novel Electronic Design Automation (EDA) tool designed to automate the confidentiality verification of sensitive data across the hardware-software boundary in embedded processors. It identifies whether specific software exploits existing

By Admin 4 Aug 2023 • 2 min read •

Research

SafeLS: Toward Building a Lockstep NOEL-V Core (Full Report)

By Admin 28 Jul 2023 • 3 min read •

Research

SafeLS: Toward Building a Lockstep NOEL-V Core

Abstract This paper presents SafeLS, an extension designed to integrate lockstep capabilities into Gaisler's NOEL-V RISC-V core for use in safety-critical systems. Lockstep architecture is employed to prevent Common Cause Failures

By Admin 28 Jul 2023 • 1 min read •

Research

SafeTI Traffic Injector Enhancement for Effective Interference Testing in Critical Real-Time Systems (Full Report)

By Admin 28 Jul 2023 • 3 min read •

Research

SafeTI Traffic Injector Enhancement for Effective Interference Testing in Critical Real-Time Systems

Abstract Safety-critical systems utilizing powerful multicores must rigorously validate mutual interference arising from shared hardware resources. This paper introduces significant enhancements to the SafeTI traffic injector, including internal pipelining for higher-rate injection and

By Admin 28 Jul 2023 • 2 min read •

Research

Rock paper scissors: ASRock midrange A770 looks good - Jon Peddie Research

Originally published on Google News - RISC-V Research Rock paper scissors: ASRock midrange A770 looks good  Jon Peddie Research

By Admin 24 Jul 2023 •

Research

Envisioning a Safety Island to Enable HPC Devices in Safety-Critical Domains (Full Report)

By Admin 21 Jul 2023 • 3 min read •