Research
RISC-V Micro-Architectural Verification - Semiconductor Engineering
Abstract
Verifying complex, customizable RISC-V cores at the micro-architectural level presents significant challenges, moving beyond simple ISA compliance to confirm the functional correctness of features like pipelines and caches. The article
Research
Branch Prediction in Hardcaml for a RISC-V 32im CPU
Abstract
This paper presents a hardware implementation of aggressive branch prediction techniques for a high-performance RISC-V 32im CPU core. The methodology progresses from simple static decode stage predictions to the utilization
Research
Examining China’s Grand Strategy For RISC-V - The Jamestown Foundation
Abstract
The article examines China’s comprehensive national strategy to leverage the open-source RISC-V instruction set architecture (ISA) as a critical path toward technological self-sufficiency and mitigating the impact of
Research
32-Bit RISC-V CPU Core on Logisim
Abstract
This project details the successful design and implementation of a 32-bit RISC-V CPU Core utilizing the Logisim digital logic simulation software. The effort capitalizes on the open-standard, royalty-free
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Fast Interrupt Extension For MCU RISC-V - Semiconductor Engineering
Abstract
Semiconductor Engineering analyzes a proposed Fast Interrupt Extension designed specifically for RISC-V Microcontroller Units (MCUs). This crucial innovation aims to significantly reduce interrupt latency, addressing the high overhead associated with standard
Research
Secure Instruction and Data-Level Information Flow Tracking Model for RISC-V
Abstract
This study proposes a novel multi-level granularity Information Flow Tracking (IFT) model designed specifically for the RISC-V architecture to enhance runtime security and system integrity. The approach integrates hardware-based