Research
A Heterogeneous RISC-V based SoC for Secure Nano-UAV Navigation
Abstract
The Shaheen SoC is a 9mm² heterogeneous RISC-V based processor designed to enable secure and autonomous navigation for energy-constrained nano-UAVs, addressing the need for advanced ML capabilities and secure operating system co-existence.
Research
TitanCFI: Toward Enforcing Control-Flow Integrity in the Root-of-Trust
Abstract
TitanCFI is a novel architecture designed to enforce Control-Flow Integrity (CFI) within the Root-of-Trust (RoT) on modern RISC-V platforms, mitigating attacks that divert control flow. This approach modifies the protected core'
Research
3 trends for 2024: AI drives more edge intelligence, RISC-V, & chiplets - embedded.com
Abstract
The embedded technology landscape for 2024 is being rapidly reshaped by the confluence of three major trends: the expansion of AI processing to the edge, the increasing ubiquity and maturity of the
Research
Algorithms for Improving the Automatically Synthesized Instruction Set of an Extensible Processor
Abstract
This paper introduces novel algorithms designed to optimize the automatically synthesized instruction sets (ISAs) used in extensible processors and hardware accelerators like RISC-V. The methods include a Common Operations Clustering algorithm to
Research
RHS-TRNG: A Resilient High-Speed True Random Number Generator Based on STT-MTJ Device
Abstract
The RHS-TRNG is a novel True Random Number Generator utilizing the stochastic switching characteristics of Spin-Transfer Torque Magnetic Tunnel Junction (STT-MTJ) devices to deliver high-quality randomness. This design achieves exceptional speed, reaching
Research
Siracusa: A 16 nm Heterogenous RISC-V SoC for Extended Reality with At-MRAM Neural Engine
Abstract
Siracusa is a 16 nm heterogeneous RISC-V System-on-Chip designed for latency- and power-constrained Extended Reality (XR) applications requiring intensive Machine Learning. The key innovation is the tightly-coupled "At-Memory" integration of