Research

A Mess of Memory System Benchmarking, Simulation and Application Profiling

Abstract The Memory stress (Mess) framework provides a unified, open-source solution for memory system benchmarking, accurate simulation, and application profiling using holistic bandwidth–latency curves. This benchmark characterizes a wide array of high-end

By Admin 16 May 2024 • 2 min read •

Research

SentryCore: A RISC-V Co-Processor System for Safe, Real-Time Control Applications (Full Report)

By Admin 16 May 2024 • 3 min read •

Research

SentryCore: A RISC-V Co-Processor System for Safe, Real-Time Control Applications

Abstract SentryCore is a reliable, open-source RISC-V co-processor system (mega-IP) designed for advanced, real-time control functions in safety-critical applications like automotive and robotics. It ensures reliability by using three embedded RISC-V cores operating

By Admin 16 May 2024 • 2 min read •

Research

Basilisk: Achieving Competitive Performance with Open EDA Tools on an Open-Source Linux-Capable RISC-V SoC (Full Report)

By Admin 6 May 2024 • 3 min read •

Research

Basilisk: Achieving Competitive Performance with Open EDA Tools on an Open-Source Linux-Capable RISC-V SoC

Abstract The paper introduces Basilisk, an optimized application-specific integrated circuit (ASIC) implementation built upon the open-source Iguana RISC-V SoC, demonstrating a highly effective open-source electronic design automation (EDA) flow. By enhancing synthesis tools

By Admin 6 May 2024 • 2 min read •

Research

PCG: Mitigating Conflict-based Cache Side-channel Attacks with Prefetching (Full Report)

By Admin 6 May 2024 • 3 min read •

Research

PCG: Mitigating Conflict-based Cache Side-channel Attacks with Prefetching

Abstract PCG is a novel prefetching-based scheme designed to effectively mitigate conflict-based cache side-channel attacks without incurring significant performance penalties. It achieves robust security by generating noisy, indistinguishable cache access patterns through a

By Admin 6 May 2024 • 2 min read •

Research

STRELA: STReaming ELAstic CGRA Accelerator for Embedded Systems (Full Report)

By Admin 18 Apr 2024 • 3 min read •

Research

STRELA: STReaming ELAstic CGRA Accelerator for Embedded Systems

Abstract STRELA is an elastic Coarse-Grained Reconfigurable Architecture (CGRA) integrated into an energy-efficient RISC-V System-on-Chip (SoC) designed for the embedded domain. Its microarchitecture specifically supports conditionals and irregular loops, enhancing adaptability for complex,

By Admin 18 Apr 2024 • 2 min read •

Research

Reconfigurable Edge Hardware for Intelligent IDS: Systematic Approach (Full Report)

By Admin 13 Apr 2024 • 3 min read •

Research

Reconfigurable Edge Hardware for Intelligent IDS: Systematic Approach

Abstract This paper addresses the deployment of intelligent Intrusion Detection Systems (I-IDS) on resource-constrained Edge hardware by proposing a systematic approach utilizing reconfigurable FPGA technology. The authors implemented and compared two architectures: a

By Admin 13 Apr 2024 • 2 min read •

Research

Beyond Random Inputs: A Novel ML-Based Hardware Fuzzing (Full Report)

By Admin 10 Apr 2024 • 3 min read •