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Occamy: A 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Floating-Point Support in 12nm FinFET

Originally published on ArXiv - Hardware Architecture Abstract We present Occamy, a 432-core RISC-V dual-chiplet 2.5D system for efficient sparse linear algebra and stencil computations on FP64 and narrow (32-, 16-, 8-bit)

By Admin 21 Jun 2024 • 1 min read •

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RISC-V processor enhanced with a dynamic micro-decoder unit (Full Report)

By Admin 21 Jun 2024 • 3 min read •

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RISC-V processor enhanced with a dynamic micro-decoder unit

Abstract This paper assesses the benefits and costs of integrating a CISC-inspired dynamic micro-decoding unit into a standard RISC-V processor core. The unit is designed to sit within a specific pipeline stage, enabling

By Admin 21 Jun 2024 • 1 min read •

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Scalable and RISC-V Programmable Near-Memory Computing Architectures for Edge Nodes (Full Report)

By Admin 20 Jun 2024 • 3 min read •

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Scalable and RISC-V Programmable Near-Memory Computing Architectures for Edge Nodes

Abstract This paper presents a novel, software-friendly Near-Memory Computing (NMC) approach, featuring two scalable RISC-V programmable architectures, NM-Caesar and NM-Carus, designed to enhance energy efficiency in AI-driven edge nodes. These architectures offer low

By Admin 20 Jun 2024 • 2 min read •

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Optimising GPGPU Execution Through Runtime Micro-Architecture Parameter Analysis (Full Report)

By Admin 14 Jun 2024 • 3 min read •

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Optimising GPGPU Execution Through Runtime Micro-Architecture Parameter Analysis

Abstract This work tackles the limitations of proprietary GPGPU analysis tools by leveraging open-source hardware to enable deep micro-architecture parameter analysis. The authors introduce a hardware-aware, runtime mapping technique for OpenCL kernels validated

By Admin 14 Jun 2024 • 2 min read •

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Rowhammer Bit Flips On A High-End RISC-V CPU (ETH Zurich) - Semiconductor Engineering (Full Report)

By Admin 13 Jun 2024 •

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Rowhammer Bit Flips On A High-End RISC-V CPU (ETH Zurich) - Semiconductor Engineering

Abstract Researchers from ETH Zurich successfully demonstrated the Rowhammer vulnerability, achieving memory bit flips, on a modern, high-end RISC-V CPU platform. This finding confirms that memory interference attacks are applicable beyond traditional architectures

By Admin 13 Jun 2024 • 2 min read •

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Hypervisor Extension for a RISC-V Processor (Full Report)

By Admin 12 Jun 2024 • 2 min read •

Research

Hypervisor Extension for a RISC-V Processor

Abstract This paper documents the practical experience of implementing a Hypervisor extension specifically tailored for a 64-bit RISC-V processor architecture. The authors detail the comprehensive design process required to integrate virtualization support into

By Admin 12 Jun 2024 • 1 min read •

Research

A 0.96pJ/SOP, 30.23K-neuron/mm^2 Heterogeneous Neuromorphic Chip With Fullerene-like Interconnection Topology for Edge-AI Computing (Full Report)

By Admin 3 Jun 2024 • 3 min read •