Abstract
The 61st Design Automation Conference (DAC 61) centered on how Electronic Design Automation (EDA) tools are evolving to tackle the exponentially growing complexity of modern electronic systems. Innovations focused heavily on managing
Abstract
This paper introduces the RISC-V R-extension, a novel architectural approach designed to enhance Deep Neural Network (DNN) processing efficiency on lightweight edge devices. The R-extension avoids the high power, cost, and area
Abstract
The AI-PiM project introduces a novel extension to the RISC-V processor architecture by integrating specialized Processing-in-Memory (PiM) functional units. This architectural enhancement is specifically designed to accelerate Artificial Intelligence (AI) inference tasks
Abstract
The NoX processor is a compact, open-source, 32-bit RISC-V core designed in System Verilog to serve as a plug-and-play solution for Multi-Processor Systems-on-Chip (MPSoCs) targeting edge computing and IoT applications. It utilizes
Abstract
The paper details the design, implementation, and evaluation of the RISC-V SVNAPOT Extension, intended to reduce Memory Management Unit (MMU) overhead during heavy memory loads. This extension leverages larger 64KB Natural-Power-of-Two (NAPOT)
Abstract
Basilisk is presented as the first end-to-end open-source, Linux-capable RISC-V System-on-Chip (SoC), successfully taped out utilizing IHP's open 130 nm CMOS technology. This achievement validates the capability of open-source hardware