Research

Exploiting long vectors with a CFD code: a co-design show case

Abstract This paper showcases a co-design methodology utilizing iterative analysis and compiler autovectorization to effectively exploit long vector architectures in HPC applications, specifically a production CFD code. The optimization process, designed to maximize

By Admin 27 Oct 2024 • 2 min read •

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Open-Source, Chiplet-Compatible RISC-V Controller - Semiconductor Engineering (Full Report)

By Admin 22 Oct 2024 •

Research

Open-Source, Chiplet-Compatible RISC-V Controller - Semiconductor Engineering

Abstract This article details the release of a new open-source RISC-V controller specifically engineered for compatibility with modern chiplet architectures. The innovation provides a modular, accessible solution for managing complex control functions within

By Admin 22 Oct 2024 • 2 min read •

Research

ControlPULPlet: A Flexible Real-time Multi-core RISC-V Controller for 2.5D Systems-in-package (Full Report)

By Admin 21 Oct 2024 • 3 min read •

Research

ControlPULPlet: A Flexible Real-time Multi-core RISC-V Controller for 2.5D Systems-in-package

Abstract ControlPULPlet is an open-source, real-time multi-core RISC-V controller designed specifically to manage coupled operation within 2.5D Systems-in-Package (SiP). The architecture minimizes performance penalties from die-to-die communication by integrating a 32-bit CV32RT

By Admin 21 Oct 2024 • 2 min read •

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Per-Bank Bandwidth Regulation of Shared Last-Level Cache for Real-Time Systems (Full Report)

By Admin 17 Oct 2024 • 3 min read •

Research

Per-Bank Bandwidth Regulation of Shared Last-Level Cache for Real-Time Systems

Abstract This paper addresses critical timing predictability issues in multicore real-time systems caused by cache bank contention and malicious bank-aware Denial-of-Service (DoS) attacks in shared Last-Level Caches (LLCs). The authors propose a novel

By Admin 17 Oct 2024 • 2 min read •

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Work-in-Progress: Real-Time Neural Network Inference on a Custom RISC-V Multicore Vector Processor (Full Report)

By Admin 14 Oct 2024 • 3 min read •

Research

Work-in-Progress: Real-Time Neural Network Inference on a Custom RISC-V Multicore Vector Processor

Abstract This work presents a custom RISC-V multicore vector processor architecture combined with a novel compiler-based deployment toolchain tailored for real-time neural network inference. The design addresses the gap between high-performance accelerators (which

By Admin 14 Oct 2024 • 2 min read •

Research

RISC-V Needs Secure 'Wheels': the MCU Initiator-Side Perspective (Full Report)

By Admin 13 Oct 2024 • 3 min read •

Research

RISC-V Needs Secure 'Wheels': the MCU Initiator-Side Perspective

Abstract This paper critically analyzes the limitations of current RISC-V Instruction Set Architectures (ISA), including the upcoming WorldGuard technology, in meeting the strict cyber-security requirements of modern, virtualized automotive microcontroller units (MCUs) mandated

By Admin 13 Oct 2024 • 2 min read •

Research

RISC-V Needs Secure 'Wheels': the MCU Initiator-Side Perspective

Originally published on ArXiv - Hardware Architecture Computer Science > Cryptography and Security arXiv:2410.09839v1 (cs) [Submitted on 13 Oct 2024] Title:RISC-V Needs Secure 'Wheels': the MCU Initiator-Side Perspective

By Admin 13 Oct 2024 • 5 min read •