Research

Multi-Dimensional Vector ISA Extension for Mobile In-Cache Computing

Abstract This paper introduces the Multi-dimensional Vector ISA Extension (MVE) designed specifically for mobile In-Cache Computing (ICC), addressing the inefficiency of existing 1D vector ISAs like RVV when utilizing wide SIMD units. MVE

By Admin 17 Jan 2025 • 2 min read •

Research

Occamy: A 432-Core Dual-Chiplet Dual-HBM2E 768-DP-GFLOP/s RISC-V System for 8-to-64-bit Dense and Sparse Computing in 12nm FinFET (Full Report)

By Admin 13 Jan 2025 • 4 min read •

Research

Occamy: A 432-Core Dual-Chiplet Dual-HBM2E 768-DP-GFLOP/s RISC-V System for 8-to-64-bit Dense and Sparse Computing in 12nm FinFET

Abstract Occamy is a 432-core, 768-DP-GFLOP/s, dual-chiplet RISC-V system designed specifically to maximize compute efficiency across both dense and sparse FP8-to-FP64 ML and HPC workloads. Utilizing dual-HBM2E memory, a latency-tolerant interconnect, and

By Admin 13 Jan 2025 • 2 min read •

Research

Modern Hardware Security: A Review of Attacks and Countermeasures (Full Report)

By Admin 8 Jan 2025 • 3 min read •

Research

Modern Hardware Security: A Review of Attacks and Countermeasures

Abstract This paper reviews the urgent state of hardware security, driven by the proliferation of cloud, IoT, and smart devices, and the rapid evolution of computing architectures. It provides a comprehensive analysis of

By Admin 8 Jan 2025 • 2 min read •

Research

Mixed-Level Modeling and Evaluation of a Cache-less Grid of Processing Cells (Full Report)

By Admin 19 Dec 2024 •

Research

Mixed-Level Modeling and Evaluation of a Cache-less Grid of Processing Cells

Abstract This article introduces a novel architecture based on a cache-less grid composed of numerous processing cells, designed to maximize parallelism and efficiency for embedded applications. The core innovation lies in utilizing a

By Admin 19 Dec 2024 • 2 min read •

Research

A Flexible Template for Edge Generative AI with High-Accuracy Accelerated Softmax & GELU (Full Report)

By Admin 9 Dec 2024 • 3 min read •

Research

A Flexible Template for Edge Generative AI with High-Accuracy Accelerated Softmax & GELU

Abstract This paper introduces a BFloat16 RISC-V acceleration template for edge Generative AI, specifically addressing the performance bottleneck caused by softmax and GELU non-linearities in Transformer models. The innovation lies in SoftEx, a

By Admin 9 Dec 2024 • 2 min read •

Research

Efficient transformer adaptation for analog in-memory computing via low-rank adapters (Full Report)

By Admin 26 Nov 2024 • 3 min read •

Research

Efficient transformer adaptation for analog in-memory computing via low-rank adapters

Abstract This paper proposes Analog Hardware-Aware Low-Rank Adaptation (AHWA-LoRA) to efficiently adapt large transformer models for Analog In-Memory Computing (AIMC) hardware, circumventing the need for costly full model retraining or analog device reprogramming.

By Admin 26 Nov 2024 • 2 min read •

Research

From CISC to RISC: language-model guided assembly transpilation (Full Report)

By Admin 25 Nov 2024 • 3 min read •