Test Post
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Test Post 3
Another test post about RISC-V processors.
Research
Efficient Trace for RISC-V: Design, Evaluation, and Integration in CVA6
Abstract
This work presents the design and evaluation of a Processor Tracing System compliant with the RISC-V Efficient Trace specification for Instruction Branch Tracing. Integrated into the CVA6 edge architecture, the system was
Research
Register Dispersion: Reducing the Footprint of the Vector Register File in Vector Engines of Low-Cost RISC-V CPUs
Abstract
The large area consumption of the Vector Register File (VRF) in RISC-V vector engines hinders their deployment in low-cost CPUs designed for edge Machine Learning acceleration. This paper introduces "Register Dispersion,
Research
Work-In-Progress: Accelerating Numpy With OpenBLAS For Open-Source RISC-V Chips
Abstract
This preliminary work presents a methodology for accelerating high-level Python applications, specifically those utilizing the Numpy library, on heterogeneous RISC-V Systems-on-Chip (SoCs). The approach involves modifying the OpenBLAS library to utilize OpenMP
Research
Fused-Tiled Layers: Minimizing Data Movement on RISC-V SoCs with Software-Managed Caches
Abstract
This work introduces Fused-Tiled Layers (FTL), a novel algorithm designed for the automatic fusion of tiled layers in Deep Neural Networks (DNNs) to minimize excessive data movement. FTL addresses the common issue
Research
MemPool Flavors: Between Versatility and Specialization in a RISC-V Manycore Cluster
Originally published on ArXiv - Hardware Architecture
Computer Science > Hardware Architecture
arXiv:2504.03675v1 (cs)
[Submitted on 21 Mar 2025]
Title:MemPool Flavors: Between Versatility and Specialization in a RISC-V Manycore Cluster