News
Will RISC-V reduce auto MCU’s future risk? – Monthly Billet - Yole Group
Abstract
Yole Group analyzes the potential of the open-source RISC-V instruction set architecture (ISA) to mitigate critical supply chain and design risks currently facing the proprietary automotive microcontroller (MCU) market. The analysis suggests
News
A RISC-V 32-bit microprocessor based on two-dimensional semiconductors - Nature
Abstract
This Nature publication reports the successful fabrication of a functional 32-bit RISC-V microprocessor utilizing two-dimensional (2D) semiconductors. This achievement demonstrates the viability of integrating novel low-dimensional materials into complete, industry-standard computing architectures.
Research
WebRISC-V: A 64-bit RISC-V Pipeline Simulator for Computer Architecture Classes
Abstract
WebRISC-V is a new web-based educational simulator designed to visualize the pipelined execution of 64-bit RISC-V assembly programs, adhering to the RV64IM specification. The tool allows users to inspect the internal state
Research
CIMR-V: An End-to-End SRAM-based CIM Accelerator with RISC-V for AI Edge Device
Abstract
CIMR-V is an end-to-end SRAM-based Computing-in-Memory (CIM) accelerator integrated with a RISC-V core designed specifically for AI edge devices. The architecture addresses the long latency associated with loading large models from DRAM
Research
Late Breaking Results: A RISC-V ISA Extension for Chaining in Scalar Processors
Abstract
Modern accelerators relying on scalar in-order cores often suffer from pipeline stalls, an issue traditionally mitigated by loop unrolling which increases undesirable register pressure. This work introduces 'scalar chaining,' a
Research
Dual-Issue Execution of Mixed Integer and Floating-Point Workloads on Energy-Efficient In-Order RISC-V Cores
Abstract
This paper introduces the COPIFT methodology and associated RISC-V ISA extensions to enable low-cost, flexible dual-issue execution on energy-efficient in-order cores. Designed to accelerate mixed integer and floating-point workloads common in modern